GLSVLSI 2023

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Keynote 1: Smart Healthcare

 
Abstract:The Internet-of-Things (IoT) era promises hundreds of billions of devices or physical objects connected to the Internet. These objects include sensors, actuators, and processing elements that help us gather data, make intelligent decisions, and optimize processes. IoT is expected to have a potential economic impact of $3-6 trillion per year by 2025, with $1-2.5 trillion of this economic impact (its largest fraction) coming from smart healthcare applications. These healthcare applications will be enabled by various technologies, e.g., (i) neural network based detection and differential diagnosis using wearable medical sensors present in smartwatches and smartphones that will communicate with a health server to enable a physician to keep track of an individual’s health, (ii) image analytics, powered by accurate convolutional neural networks, with applications to radiology, pathology, ophthalmology, dermatology, cardiology, gastroenterology, etc., and (iii) personalized medical decision-making. However, many challenges remain in making this vision a reality. In this talk, we will explore how machine learning models employed at different layers of the healthcare hierarchy can begin to realize the above vision.
 
Bio: Niraj K. Jha received his B.Tech. degree in Electronics and Electrical Communication Engineering from Indian Institute of Technology, Kharagpur, India in 1981 and Ph.D. degree in Electrical Engineering from University of Illinois at Urbana-Champaign in 1985. He is a Professor of Electrical and Computer Engineering at Princeton University. He has served as an Associate Director for the Princeton Andlinger Center for Energy and the Environment. He is a Fellow of IEEE and ACM. He was given a Distinguished Alumnus Award by I.I.T., Kharagpur in 2014. He has co-authored five books among which are two textbooks that are being widely used around the world. He has served as the Editor-in-Chief of IEEE Transactions on VLSI Systems and on the editorial boards of several other IEEE Transactions. He is an author or co-author of more than 470 papers among which are 15 award-winning papers. His research interests include algorithms and architectures for machine learning, with applications to smart healthcare.

Keynote 2: Closing the Gap between Quantum Algorithms and Machines with Hardware-Software Co-Design

 
Abstract: Quantum computing is at an inflection point, where 127-qubit machines are deployed, and 1000-qubit machines are only a few years away.These machines have the potential to fundamentally change our concept of what is computable and demonstrate practical applications in areas such as quantum chemistry, optimization, and quantum simulation.
Yet a significant resource gap remains between practical quantum algorithms and real machines. A promising approach to closing this gap is to design software that is aware of the key physical properties of emerging quantum technologies. I will illustrate this approach with some of our recent work that focuses on techniques that break traditional abstractions and inform hardware design, including compiling programs directly to analog control pulses, computing with ternary quantum bits, 2.5D architectures for surface codes, and exploiting long-distance communication and tolerating atom loss in neutral-atom machines.
 
Bio: Fred Chong is the Seymour Goodman Professor in the Department of Computer Science at the University of Chicago and the Chief Scientist for Quantum Software at Infleqtion. He is also Lead Principal Investigator for the EPiQC Project (Enabling Practical-scale Quantum Computing), an NSF Expedition in Computing. Chong is a member of the National Quantum Advisory Committee (NQIAC) which provides advice to the President on the National Quantum Initiative Program. In 2020, he co-founded Super.tech, a quantum software company, which was acquired by Infleqtion (formerly ColdQuanta) in 2022. Chong received his Ph.D. from MIT in 1996 and was a faculty member and Chancellor's fellow at UC Davis from 1997-2005. He was also a Professor of Computer Science, Director of Computer Engineering, and Director of the Greenscale Center for Energy-Efficient Computing at UCSB from 2005-2015. He is a fellow of the IEEE and a recipient of the NSF CAREER award, the Intel Outstanding Researcher Award, and 13 best paper awards.

Keynote 3: Microelectronics Security in CHIPS Era

 
Abstract: The CHIPS Act has brought much needed excitement for onshoring/reshoring the front-end and back-end fabrication test and facilities. However, much of the security concerns during the design of modern system on chips (SoCs) or system-in-package (SiPs) have little to do with onshoring. This talk will discuss challenges to securing silicon development lifecycle with CHIPS in place, offer solutions to engineers and practitioners, and present research challenges and opportunities for academics.
Bio: Mark M. Tehranipoor is currently the Intel Charles E. Young Preeminence Endowed Chair Professor and the Chair of the Department of Electrical and Computer Engineering (ECE) at the University of Florida. His current research projects include: hardware security and trust, supply chain security, IoT security, VLSI design, test and reliability. He has 21 patents, 18 books, and 500+ conference/journal publications. He is a recipient of 17 best paper awards and nominations, as well as the 2008 IEEE Computer Society (CS) Meritorious Service Award, the 2012 IEEE CS Outstanding Contribution, the 2009 NSF CAREER Award, and the 2014 AFOSR MURI award. He received the 2020 University of Florida Innovation of the year as well as teacher/scholar of the year awards. He co-founded the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE). He serves on the program committee of more than a dozen leading conferences and workshops. He has also served as Program and General Chair of a number of IEEE and ACM sponsored conferences and workshops (HOST, ITC, DFT, D3T, DBT, NATW, and more). He is currently serving as a founding EIC for Journal on Hardware and Systems Security (HaSS) and served as Associate Editor for TC, JETTA, JOLPE, TODAES, IEEE D&T, TVLSI. He is currently serving as a founding director for Florida Institute for Cybersecurity Research (FICS) and a number of other centers with focus on microelectronics security. Dr. Tehranipoor is a Fellow of the IEEE, a Fellow of the ACM, a Fellow of the National Academy of Inventors (NAI), a Golden Core Member of IEEE CS, and Member of ACM SIGDA.

Keynote 4: Hardware Security from the Information Perspective

 
Abstract: Hardware security has received a lot of attention since 1996. This keynote provides a comprehensive view of the fundamental problems in hardware security to help integrated circuit (IC) designers and security researchers understand the security vulnerabilities in microelectronics supply chain, the available mitigations, the challenges and research opportunities. We consider hardware security as the study and implementation of protection for circuit design and fabrication, data storage and processing, as well as systems and sub-systems built on hardware. Based on this definition, key problems in hardware security can be categorized as intellectual property (IP) protection, secure storage and execution, and hardware security primitives. We present these problems and the corresponding solutions from a novel perspective of information battle between the attackers and designers where three types of information are involved: data collected, processed, and stored by the hardware; information hidden in the design as watermark, fingerprint, and Trojans; as well as chip fabrication variations and other physical features that can be extracted and utilized. Open problems and potential research directions will also be analyzed under this unified framework of information battle.
Bio: Dr. Gang Qu is a professor in the Department of Electrical and Computer Engineering at the University of Maryland, College Park. He has worked extensively in the areas of hardware security and low power design. He has made significant contribution in building the hardware security and trust community. Notably, he was an individual member of the VSIA intellectual property protection (IPP) development working group (2001) and contributed to VSIA’s IPP standards; he published the first book (2003) on hardware security, Intellectual Property Protection in VLSI Designs: Theory and Practice, based on his Ph.D. dissertation (2000); he developed a MOOC of hardware security on Coursera (2014); he co-founded the AsianHOST symposium (2016) and the IEEE CEDA hardware security and trust technique committee (HSTTC, 2020). Since October 2021, he has been working as a program director in the NSF Secure and Trustworthy Cyberspace (SaTC) program. He is a fellow of IEEE.

Keynote 5: 20 Years After: New Thermal Challenges in Circuit Design and Architecture

 
Abstract: This keynote will offer future thermal research directions from the perspective of HotSpot, the most widely used open-source thermal modeling tool. HotSpot is 20 years old now (incidentally, there are also exactly 20 years since the keynote speaker was general chair for GLSVLSI 2003). The HotSpot original contributions were to recognize the need for thermal models to be "physical" in order to explore both spatial and temporal thermal variations and for the thermal tools to be compatible with the available design tools infrastructure. The keynote speaker is a circuit designer at heart and this influenced the original HotSpot thermal model: the model was based on a widely known electrical analogy for heat transfer that can be used to transform a complex 3D thermal model into a simpler thermal circuit with thermal resistances and thermal capacitances then solved using circuit solvers. Since the original development of HotSpot one of the significant changes has been the move to 3DIC and chiplets for which new cooling methods may be needed, particularly microfluidic cooling. Interestingly, as there is an electrical analogy of heat flow (power is analogous to electrical current, temperature is analogous to voltage, etc.), there is a similar analogy for fluid flow in which volumetric flow is analogous to electrical current and pressure is analogous to voltage. Thus one can build a circuit to model the microfluidic flow in addition to the conventional electrical circuit that represents the IC functionality and the thermal circuit that models heat flow. These three types of circuits are now part of the newest HotSpot 7.0 release. There are many needs for future thermal research, including the need for floorplans to be 2.5D and 3D floorplans, the need to model spatial variations and anisotropy due to fluidics, BEOL, TSV and bumps distribution, the need for composable thermal models with different trade-offs between accuracy and performance and the need for the architecture tools to become compatible with conventional EDA tools for validating post-RTL and post-P&R designs.
Bio: Mircea R. Stan is teaching and doing research in the areas of AI hardware, Processing in Memory, Cyber-Physical Systems, Computational RFID, spintronics, and nanoelectronics. Since 1996 he has been with the ECE Department at UVa, where he is now the Virginia Microelectronics Consortium (VMEC) endowed chair and Director of Computer Engineering. He received the 2018 Influential ISCA Paper Award for the 2003 best paper “Temperature-aware microarchitecture”. He is Editor-in-Chief for the IEEE TVLSI and was general chair for GLSVLSI 2003. Prof. Stan is a fellow of the IEEE.

Invited Talk: Graph States and the Challenges for Efficient Quantum Circuit Compilation

 
Abstract: Graphs can be used as a diagrammatic representation of entangled states: vertices represent qubits, and edges are the entangling gates performed between the qubits. Arbitrary quantum circuits can be compiled into a fault-tolerant gate set, and the resulting circuit can be reformulated as a graph state. Such graphs can be manipulated by local operations (single qubit/vertex gates) such that edges are added and removed in a well defined manner during a process called local complementation. The latter might have interesting applications for the optimisation of (fault-tolerant) quantum circuits, quantum communication networks and in general whenever, either: a) there is a need to minimize the number of edges (entangling gates) without affecting the functionality of the state, or b) the state has to be embedded into a quantum hardware architecture that has a different connectivity. This talk is partially based on the work from https://arxiv.org/abs/2209.07345.
Bio: Alexandru Paler is an assistant professor at Aalto University, Espoo, Finland. His research interests are on the aspects of fault-tolerant quantum computation, especially wrt surface code architectures: compilers, optimization methods and decoder implementations. He co-authored one of the first papers related to NISQ compilation for IBM computers and recently co-developed methods on how to use surface codes on restricted architectures or non-standard way. He is leading the quantum algorithms and software research group at Aalto University, and is the PI of two projects in the DARPA Quantum Benchmarking programme, in the QuantERA EQUIP project, and some national projects.

Technical Session 1A

Technical Session 1B

Technical Session 2A

Technical Session 2B

Technical Session 3A

Technical Session 3B

Technical Session 4A

Technical Session 4B

Technical Session 5A

Technical Session 5B

Technical Session 6A

Technical Session 6B

Technical Session 7A

Technical Session 7B

Special Session 1

Special Session 2

Special Session 3

Special Session 4

Special Session 5

Special Session 6

Special Session 7

Panel Session 1

Panel Session 2

Poster Session 1

Poster Session 2

Panelists

Menon Vivek

 
Bio: Vivek Menon is the Mission Assurance Director in the Systems Engineering Directorate at the National Reconnaissance Office. He is responsible for the Microelectronics roadmap and strategy for NRO. His research interests are in microelectronics security, zero knowledge proofs, zero-trust architecture, and supply chain provenance. He is a Senior Member of IEEE and received his Ph.D. in Computer Engineering from Virginia Tech.

Mark Tehranipoor

 
Bio: Mark M. Tehranipoor is currently the Intel Charles E. Young Preeminence Endowed Chair Professor and the Chair of the Department of Electrical and Computer Engineering (ECE) at the University of Florida. His current research projects include: hardware security and trust, supply chain security, IoT security, VLSI design, test and reliability. He has 21 patents, 18 books, and 500+ conference/journal publications. He is a recipient of 17 best paper awards and nominations, as well as the 2008 IEEE Computer Society (CS) Meritorious Service Award, the 2012 IEEE CS Outstanding Contribution, the 2009 NSF CAREER Award, and the 2014 AFOSR MURI award. He received the 2020 University of Florida Innovation of the year as well as teacher/scholar of the year awards. He co-founded the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE). He serves on the program committee of more than a dozen leading conferences and workshops. He has also served as Program and General Chair of a number of IEEE and ACM sponsored conferences and workshops (HOST, ITC, DFT, D3T, DBT, NATW, and more). He is currently serving as a founding EIC for Journal on Hardware and Systems Security (HaSS) and served as Associate Editor for TC, JETTA, JOLPE, TODAES, IEEE D&T, TVLSI. He is currently serving as a founding director for Florida Institute for Cybersecurity Research (FICS) and a number of other centers with focus on microelectronics security. Dr. Tehranipoor is a Fellow of the IEEE, a Fellow of the ACM, a Fellow of the National Academy of Inventors (NAI), a Golden Core Member of IEEE CS, and Member of ACM SIGDA.

Anne Matsuura

 
Bio: Dr. Anne Matsuura is the Director of Quantum Applications & Architecture at Intel Labs. Her team focuses on creating algorithms and the system architecture for quantum computing systems Previously, she held positions as the Chief Scientist of the Optical Society (OSA) and the Chief Executive of the European Theoretical Spectroscopy Facility (ETSF). She has been a strategic investor in technology start-ups at In-Q-Tel, a funder of basic science at the Air Force Office of Scientific Research, and has experience as a science policymaker as a special assistant to the U.S. Deputy Under Secretary of Defense for Laboratories and Basic Science. Anne was the recipient of a Fulbright Scholarship to Japan and is an elected fellow of the OSA. Anne received her Ph.D. in physics from Stanford University.

Fred Chong

 
Bio: Fred Chong is the Seymour Goodman Professor in the Department of Computer Science at the University of Chicago and the Chief Scientist for Quantum Software at Infleqtion. He is also Lead Principal Investigator for the EPiQC Project (Enabling Practical-scale Quantum Computing), an NSF Expedition in Computing. Chong is a member of the National Quantum Advisory Committee (NQIAC) which provides advice to the President on the National Quantum Initiative Program. In 2020, he co-founded Super.tech, a quantum software company, which was acquired by Infleqtion (formerly ColdQuanta) in 2022. Chong received his Ph.D. from MIT in 1996 and was a faculty member and Chancellor's fellow at UC Davis from 1997-2005. He was also a Professor of Computer Science, Director of Computer Engineering, and Director of the Greenscale Center for Energy-Efficient Computing at UCSB from 2005-2015. He is a fellow of the IEEE and a recipient of the NSF CAREER award, the Intel Outstanding Researcher Award, and 13 best paper awards.

Gang Qu

 
Bio: Dr. Gang Qu is a professor in the Department of Electrical and Computer Engineering at the University of Maryland, College Park. He has worked extensively in the areas of hardware security and low power design. He has made significant contribution in building the hardware security and trust community. Notably, he was an individual member of the VSIA intellectual property protection (IPP) development working group (2001) and contributed to VSIA’s IPP standards; he published the first book (2003) on hardware security, Intellectual Property Protection in VLSI Designs: Theory and Practice, based on his Ph.D. dissertation (2000); he developed a MOOC of hardware security on Coursera (2014); he co-founded the AsianHOST symposium (2016) and the IEEE CEDA hardware security and trust technique committee (HSTTC, 2020). Since October 2021, he has been working as a program director in the NSF Secure and Trustworthy Cyberspace (SaTC) program. He is a fellow of IEEE.

Travis Humble

 
Bio: Travis Humble is director of the Department of Energy’s Quantum Science Center, a Distinguished Scientist at Oak Ridge National Laboratory, and director of the lab’s Quantum Computing Institute. Travis leads the development of new quantum technologies and infrastructure to impact the DOE mission of scientific discovery. Travis is also editor-in-chief for ACM Transactions on Quantum Computing and co-chair of the IEEE Quantum Initiative. Travis holds a joint faculty appointment with the University of Tennessee Bredesen Center for Interdisciplinary Research and Graduate Education to work with students in developing energy-efficient computing solutions. Travis received a doctorate in theoretical chemistry from the University of Oregon before joining ORNL in 2005.

Len Orlando

 
Bio: Len joined Ansys in January of this year to be part of the Ansys Government Initiatives business unit as a senior business development executive. Within Ansys he focused on supporting opportunities within the federal, aerospace, and defense marketplace and pursing strategic initiatives for Mission to Microelectronics, Microelectronics Security, and multi-physics simulation synthetic augmentation for defense relevant environments. Len has over 21 years within the federal Microelectronics industry starting as a designer, then project and team lead, before pursuing research activities as a subject matter expert on DARPA, Office of the Secretary of Defense, and Air Force trust, assurance, and security related microelectronics programs.

Marco Pistoia

 
Bio: Marco Pistoia, Ph.D. is Managing Director, Distinguished Engineer, and Head of JPMorgan Chase's Global Technology Applied Research Center, where he leads the Quantum Computing and Quantum Communication areas of research. He joined JPMorgan Chase in January 2020. Formerly, he was a Senior Manager, Distinguished Research Staff Member and Master Inventor at the IBM Thomas J. Watson Research Center in New York, where he managed an international team of researchers responsible for Quantum Computing Algorithms and Applications. He is the inventor of over 250 patents, granted by the U.S. Patent and Trademark Office, and over 300 patent-pending applications. He is also the author of three books and over 400 scholarly papers published in international journals and conferences. In the course of his career, he received five distinguished paper awards from the IEEE and ACM.

Robert Basmadjian

 
Bio: Robert Basmadjian holds a Ph.D. from the University of Toulouse on data replication. After completing his doctorate, in 2009 he joined the University of Passau as a postdoctoral fellow, where he obtained his habilitation in 2019. Since then, he has been appointed as professor in the department of computer science both at the University of Passau and Clausthal University of Technology. He is currently leading the department of Computer Engineering at TU Clausthal. He has more than 10 years of experience in the fields of teaching, research and development tackling methodologies and concepts of computer science both from classical and quantum computing perspectives. His main research interests are (1) modeling, designing and optimizing quantum circuits (e.g. QRAM, arithmetic) using queuing theory, (2) variational quantum algorithm design and quantum machine learning for renewable energy sources, (3) modeling of performance-energy trade-off for HPC data centers, (4) AI-based prediction modeling for renewables. He has more than 60 scientific publications in the fields of sustainable, green and quantum computing. He was ascientific and technical contributor to EU FP7 FIT4Green and ALL4Green projects related to Demand Response in datacenters as well as technical coordinator of H2020 Electrific project. He is currently scientifically collaborating with the DARPA project “Quantifying Utility of Quantum Computers” (USA) coordinated by Rigetti in designing quantum decoder circuits using classical queuing theory.