Banff, Alberta, Canada, May 10-12, 2017

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 Program Highlights

Keynotes | Technical Sessions | Special Sessions | Poster Sessions

For a PDF file containing the Tentative Program Schedule click here! Click here to see the accepted technical papers, and here to see the accepted posters.





8:00 - 9:00

Speaker Breakfast

Speaker Breakfast

Speaker Breakfast

9:00 -10:00

Keynote 1

Speaker: Leland Chang, IBM 

Keynote 2

Speaker: Niraj Jha, Princeton Univ.

Keynote 4

Speaker: Alex Jones, Univ. of Pittsburgh

10:00 - 10:20

Coffee break

Coffee break

Coffee break

10:20 -12:00

Tech session 1:

Emerging Technologies and Paradigms for Low Power Computing

Tech session 2:

Design Techniques for Non-Traditional Computing

Tech session 6:

Hardware Security: New Advances in Timing Side Channel and Logic Obfuscation

Tech session 7:

Testing and Reliability


Tech session 9:

CAD under Challenges: Tight Constraints and Unreliability

Tech session 10:

Memory Design from Circuits to Architectures


12:00 -1:30

Lunch and Panel

Lunch + Keynote 3

Speaker: Andrew Putnam, Microsoft 

Lunch + Poster session 2

1:30 -2:50

Tech session 3:

Strategies for In-Memory Computing


Special session 1

Low Power Computing based on Non-Volatile Memories


Tech session 8:

Emerging Technologies, RF Circuits and Security Functions

Special session 2

Three-Dimensional Integrated Circuit Security


Special session 4

Efficient IoT Systems: The power of Heterogeneous Integration

Invited session on innovation

"Ideation and Entrepreneurship Mindset", Dr. Alex Bruton, Professor of Entrepreneurship, University of Calgary

2:50 -3:20

Coffee break + Poster session 1


Coffee break

Coffee break

3:20 - 3:50

Special session 3

Logic Obfuscation for IoT Security: A New Arms Race?

Industry - academia workshop

Innovation exchange

3:50 - 4:40


Tech session 4:

Circuits, Architectures, and System Level Issues for Many-Core Processors


Tech session 5:

CAD for the Nano Era




4:40 - 5:30

Hiking trip

5:30 - 7:00


Lake shore / Fairview look out


7:00 onwards

Cocktail Reception




 Cognitive Data-Centric Systems

Leland Chang

Senior Manager VLSI Design, IBM Research


With rapid growth in the availability of massive amounts of data and the development of new machine learning and deep learning techniques, significant opportunities exist in the application of computing to learn from data, build models, and discover insights - cognitive tasks that can augment human expertise in a broad range of industries. Computing systems must evolve to efficiently meet these needs by leveraging innovation in heterogeneous systems infrastructure and information technology consumption models that are increasingly driven by public and private cloud-based delivery. These new systems must be designed to accommodate the entirety of the overall workflow, including not just machine learning and analytics tasks, but also data management and manipulation. In a convergence with systems for classical modeling and simulation (HPC and technical computing), cognitive workloads can benefit dramatically from hardware acceleration. As decades of sustained CMOS technology scaling begins to slow, the specificity and optimality of hardware accelerators will be a key enabler for system-level performance while simultaneously presenting challenges in composing systems that seamlessly integrate traditional CPUs, multiple accelerators, and different memories. This talk will discuss cognitive data-centric systems for the next era of computing, in which balanced heterogeneous systems are delivered through the cloud.


Leland Chang is the Senior Manager of VLSI Design at the IBM T. J. Watson Research Center, where he leads a team driving the transition of new research concepts into next-generation POWER server and System Z mainframe products, including system architecture and microprocessor design implementation as well as roadmap definition and applications analysis. With a technical background spanning semiconductor technology, circuit design, system architecture, and software algorithms, his key contributions have included the FinFET structure for CMOS scaling, 8T-SRAM and high-speed register files for embedded memory scaling, integrated voltage regulators with new passive device technologies, and system design for emerging workloads such as machine learning and deep learning. He received the B. S., M. S., and Ph.D. degrees in electrical engineering and computer sciences from the University of California, Berkeley, has authored more than 75 technical articles and 115 patents, and is currently the memory subcommittee chair for the ISSCC technical program committee. 


Prof. Niraj K. Jha,
Department of Electrical Engineering, Princeton University



We have arrived at the dawn of the Internet-of-Things (IoT) era. 25 billion devices (things or physical objects) are already connected to the Internet, and this number is expected to grow to 50 billion by 2020. IoT is a network of physical objects.These objects contain sensors, actuators, and processing elements that enable us to gather data, monitor the health of the object, make intelligent decisions, and optimize processes. IoT is expected to have a potential economic impact of $3-6 trillion per year by 2025, with $1-2.5 trillion of this economic impact (its largest fraction) coming from smart healthcare applications. These applications will be enabled by a personal healthcare system consisting of implantable and wearable medical sensors and devices connected to a personal health hub (e.g., a smartphone or smartwatch) that is connected to the Internet.

In this talk, we will explore this Internet-of-Medical-Things from two angles: energy-efficient inference and security. We will first explore energy-efficient inference on sensor nodes. This exploits sparsity, which is characteristic of a signal that allows us to represent information efficiently. We will look at an approach that enables efficient representations based on sparsity to be utilized throughout a signal processing system, with the aim of reducing the energy and/or resources required for computation, communication, and storage. Such intelligent sensor nodes can be expected to be an important building block of IoT. We will then show how wearable medical sensors, which are being increasingly used as part of a body-area network to provide proactive healthcare, can be used in a completely different domain: continuous authentication, through monitoring of the biological aura of the person. Unfortunately, as with any other technology, along with the upside, we also have the downside of IoT - if the security challenges facing IoT are not addressed, it may just become an Internet-of-Things-to-be-Hacked. Hence, in the last part of the talk, we will focus on the security of a body-area network that consists of implantable/wearable medical devices and a health hub. We will also explore physiological side channels that leak information about our health condition.


Niraj K. Jha received his B.Tech. degree in Electronics and Electrical Communication Engineering from Indian Institute of Technology, Kharagpur, India in 1981 and Ph.D. degree in Electrical Engineering from University of Illinois at Urbana-Champaign in 1985. He is a Professor of Electrical Engineering at Princeton University. He has served as an Associate Director for the Princeton Andlinger Center for Energy and the Environment. He is a Fellow of IEEE and ACM. He has co-authored five books, among which are "Switching and Finite Automata Theory, 3rd ed." and "Testing of Digital Systems" that are textbooks being used around the world. He has served as the editor-in-chief of IEEE Transactions on VLSI Systems and on the editorial boards of several other IEEE Transactions. He is an author or co-author of more than 430 papers among which are 14 award-winning papers. His research interests include smart healthcare, machine learning, computer security, IoT, energy-efficient design, IC design automation, FinFETs, and monolithic 3D IC design.

FPGAs in the Datacenter - Combining the Worlds of Hardware and Software Development

Portrait of Andrew Putnam

Andrew Putnam
Microsoft Research Technologies (MSR-T) lab


The Catapult project has brought the power and performance of FPGA-based reconfigurable computing to Microsoft's hyperscale datacenters, accelerating major production cloud applications such as Bing web search and Microsoft Azure, and enabling a new generation of machine learning and artificial intelligence applications. Catapult is now deployed in nearly every new server across the more than a million machines that make up the Microsoft hyperscale cloud.


The presence of ubiquitous and programmable silicon in the datacenter ushers in a new era where the discipline and rigor of the VLSI community are combining with the speed and agility of the software community to form new opportunities in a blend development styles and techniques.


In this talk, I will describe the next generation of the Catapult configurable cloud architecture, and the tools and techniques that have made Catapult successful to date. I will also discuss areas where traditional hardware and software development flows fall short, and ways in which the VLSI community can branch into new opportunities in software and computing.



Andrew Putnam is a Principal Research Hardware Development Engineer in a collaboration between Microsoft Azure and Microsoft Research NExT. He received a dual B.A/B.S. from the University of San Diego in 2003, and an M.S. and Ph.D. in Computer Science and Engineering from the University of Washington in 2006 and 2009 respectively. His research focuses on reconfigurable computing, future datacenter design, and computer architecture, with an emphasis on seeing research through from concept to prototype to technology transfer. He was a founding member of the Microsoft Catapult project, which was the first to put Field Programmable Gate Arrays (FPGAs) into production hyperscale datacenters, doubling the capacity of each server for web search, and creating the fastest network in the cloud.

Green Computing: New Challenges and Opportunities



Alex K. Jones
University of Pittsburgh


As individuals and researchers approach the challenge of green computing it is natural to consider the energy consumption of computational devices and their supporting systems during their use phase (i.e., after they are deployed into service). This includes reducing energy consumption in processors, memory systems, peripheral devices, cooling systems and a host of other components that are used in deployed systems. However, for computing to be truly green, all phases of the system life-cycle, from manufacturing to disposal, must be considered. In particular there is limited awareness to the considerable fraction of the total life-cycle environmental impacts of computing systems that result from the fabrication of the integrated circuits (ICs) that are used in those devices. Studies have shown that the energy and environmental costs of IC fabrication can actually significantly outpace use-phase sustainability metrics and environmental impacts. With trends towards more exotic, thus, more environmentally unfriendly, fabrication approaches at deeply scaled nodes, life-cycle thinking for next generation computing systems that includes traditional optimization of operational energy-efficiency as well as minimizing impacts from IC fabrication is critical. In this talk I will present a new cadre of tools and methodologies to holistically evaluate energy consumption and other environmental impacts from computing.  Based on these tools, I will discuss new interdisciplinary research directions and educational opportunities that emerge towards achieving more sustainable computing.


Professor Alex K Jones is a MCSI Faculty Fellow in Sustainability and Director of Computer Engineering at the University of Pittsburgh. In addition to sustainable computing, his research interests include compilers, computer architectures, electronic design automation, and reliability. He is the author of more than 140 publications in these areas. His research is funded by the U.S. National Science Foundation, DARPA, CCC, the NSF CHREC center, and industry. Dr. Jones’ contributions have resulted in several awards including an ACM/SIGDA Distinguished Service Award, a seminal paper award from FCCM in addition to multiple best paper awards and nominations, a University of Pittsburgh Innovator Award, and the 2017 Carnegie Science Award. Recently, Dr. Jones led an effort in visioning for the electronic design automation community funded by the Computing Community Consortium (CCC). Dr. Jones is also actively involved in efforts to improve the scientific method for experiments in computers science and engineering, to develop methods reproducible research, and a centralized hub for computer architecture simulators, emulators, benchmarks and experiments. He serves on many journal editorial boards and conference committees including in area of sustainability, the IEEE Transactions on Sustainable Computing and the IEEE International Green and Sustainable Computing Conference. In his spare time he performs as the principal clarinetist with the Pittsburgh Philharmonic and Aeolian Winds and enjoys skiing and Tae Kwon Do.

Technical Sessions


Session 1: Emerging Technologies and Paradigms for Low Power Computing


1) Design of a Low-Power Non-Volatile Programmable Inverter Cell for COGRE-based Circuits

Fabrizio Lombardi, Pilin Junsangsri, Salin Junsangsri and Martin Margala


2) VaLHALLA: Variable Latency History Aware Local-carry Lazy Adder

Ali Murat Gok and Nikos Hardavellas


3) Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device

Hao Cai, You Wang, Lirida Naviner, Wang Kang and Weisheng Zhao


4) A Mixed-Size Monolithic 3D Placer with 2D Layout Inheritance

Xu He, Yao Wang, Yang Guo and Sorin Cotofana


5) LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks (Best Paper Candidate)

Ruizhou Ding, Zeye Liu, Rongye Shi, Diana Marculescu and Shawn Blanton


Session 2: Design Techniques for Non-Traditional Computing

1) Design of a Flash-based Circuit for Multi-valued Logic

Monther Abusultan and Sunil Khatri

2) Design of Approximate Logarithmic Multipliers
Weiqiang Liu, Jiahua Xu, Danye Wang and Fabrizio Lombardi


3) Mitigating the Effect of the Reliability Soft-errors of the RRAM Devices on the Performance of the RRAM-based Neuromorphic Systems
Amr Tosson, Shimeng Yu, Mohab Anis and Lan Wei


4) A Spin Transfer Torque based Cellular Neural Network (CNN) Architecture

Yu Bai


5) Neuro-NoC: Neural Network based Predictive Routing for Network-on-Chip Architectures

Michel Kinsy and Shreeya Khadka


Session 3: Strategies for In-Memory Computing

1) A Domain-Specific Language and Compiler for Computation-in-Memory Skeletons (Best Paper Candidate)

Jintao Yu, Tom Hogervorst and Razvan Nane

2) Energy Efficient In-Memory Computing Platform Based on 4-Terminal Spin Hall Effect-Driven Domain Wall Motion Devices

Shaahin Angizi, Zhezhi He and Deliang Fan

3) Leveraging Dual-Mode Magnetic Crossbar for Ultra-low Energy In-Memory Data Encryption

Zhezhi He, Shaahin Angizi, Farhana Parveen and Deliang Fan

4) Evaluating Data Resilience in CNNs from an Approximate Memory Perspective
Yuanchang Chen, Yizhe Zhu, Fei Qiao, Jie Han, Yuansheng Liu and Huazhong Yang



Session 4: Circuits, Architectures, and System Level Issues for Many-Core Processors


1) A Robust C-element Design with Enhanced Metastability Performance (Best Paper Candidate)

Kinshuk Sharma and Sunil Khatri


2) Circuit Level Design of a Hardware Hash Unit for use in Modern Microprocessors

Abbas Fairouz, Monther Abusultan and Sunil Khatri


3) DELCA: DVFS Efficient Low Cost Multicore Architecture

Shoumik Maiti and Sudeep Pasricha


4) EEAL: Processors' Performance Enhancement Through Early Execution of Aliased Loads

Abhishek Rajgadia, Newton Singh and Virendra Singh


5) Performance-aware resource management of multi-threaded applications on many-core systems

Daniel Olsen and Iraklis Anagnostopoulos



Session 5: CAD for the Nano Era


1) Under-the-cell Routing to Improve Manufacturability (Best Paper Candidate)

Alex Vidal-Obiols, Jordi Cortadella and Jordi Petit


2) Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains

Zhufei Chu, Xifan Tang, Mathias Soeken, Ana Petkovska, Grace Zgheib, Luca Amaru, Yinshui Xia, Paolo Ienne, Giovanni De Micheli and Pierre-Emmanuel Gaillardon


3) Redundant Via Insertion with Cut Optimization for Self-Aligned Double Patterning

Youngsoo Song, Jinwook Jung and Youngsoo Shin


4) Boolean Decomposition for AIG optimization

Lucas Machado and Jordi Cortadella


5) Mixed-Cell-Height Standard Cell Placement Legalization

Chung-Yao Hung, Peng-Yi Chou and Wai-Kei Mak



Session 6: Hardware Security: New Advances in Timing Side Channel and Logic Obfuscation


1)  Covert Timing Channels Exploiting Non-Uniform Memory Access based Architectures

Fan Yao, Guru Venkataramani and Milos Doroslovacki


2) A Low-Cost Secure GPS Spoofing Detector Design for the Internet of Things Applications (Best Paper Candidate

Md Tanvir Arafin, Dhananjay Anand and Gang Qu


3) A Novel Side-channel Timing Attack on GPUs

Zhen Hang Jiang, Yunsi Fei and David Kaeli


4) Cyclic Obfuscation for Creating SAT-Unresolvable Circuits

Kaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z. Pan and Yier Jin


5) Double DIP: Re-Evaluating Security of Logic Encryption Algorithms

Yuanqi Shen and Hai Zhou



Session 7: Testing and Reliability

1) Efficient Critical Path Selection Under a Probabilistic Delay Model (
Best Paper Candidate)

Ahish Mysore Somashekar and Spyros Tragoudas

2) Combining Restorability and Error Detection Ability for Effective Trace Signal Selection
Binod Kumar, Ankit Jindal, Masahiro Fujita and Virendra Singh


3) Radiation-Hardened Designs for Soft-Error-Rate Reduction by Delay-Adjustable D-Flip-Flops

Yuwen Lin, Charles H.-P. Wen and Herming Chiueh

4) Effective Mitigation of Radiation-induced Single Event Transient on Flash-based FPGAs
Luca Sterpone, Sarah Azimi, Boyang Du, David Merodio Codinachs and Raoul Grimoldi


5) Energy Efficient Adaptive Approach for Dependable Performance in the presence of Timing Interference

Nikolaos Zompakis, Michail Noltsis, Dimitrios Rodopoulos, Francky Catthoor and Dimitrios Soudris



Session 8: Emerging Technologies, RF Circuits and Security Functions


1) Design Automation for Paper Microfluidics with Passive Flow Substrates

Joshua Potter, William Grover and Philip Brisk


2) Neuromorphic 3D Integrated Circuit: A Hybrid, Reliable and Energy Efficient Approach for Next Generation Computing (Best Paper Candidate)

Md Amimul Ehsan, Zhen Zhou and Yang Yi


3) Method for Phase Noise Analysis of RF Circuits

Dimo Martev, Sven Hampel and Ulf Schlichtmann


4) Revealing On-chip Proprietary Security Functions with Scan Side Channel Based Reverse Engineering

Leonid Azriel, Ran Ginosar and Avi Mendelson



Session 9: CAD under Challenges: Tight Constraints and Unreliability


1) Analysis of Single Event Upsets in Combinational Designs at RTL Based on Satisfiability Modulo Theories

Ghaith Kazma, Ghaith Bany Hamad, Otmane Ait Mohamed and Yvon Savaria


2) Fine-Grain Program Snippets Generator for Mobile Core Design

Shuang Song, Raj Desikan, Mohamad Barakat, Sridhar Sundaram, Andreas Gerstlauer and Lizy K. John


3) Coupling-Aware Functional Timing Analysis for Tighter Bounds: How Much Margin Can We Relax?

Jack S.-Y. Lin, Louis Y.-Z. Lin, Ryan H.-M. Huang and Charles H.-P. Wen


4) Thermal Constrained Energy Efficient Real-Time Scheduling on Multi-Core Platforms

Shi Sha, Wujie Wen, Shaolei Ren and Gang Quan


5) Quantitative Modeling of Thermo-Optic Effects in Optical Networks-on-Chip

Weichen Liu, Peng Wang, Mengquan Li, Yiyuan Xie and Nan Guan



Session 10: Memory Design from Circuits to Architectures


1) A Reconfigurable Replica Bitline to Determine Optimum SRAM Sense Amplifier Set Time

Samira Ataei and James Stine


2) Building a Fast and Power Efficient Inductive Charge Pump System for 3D Stacked Phase Change Memories

Lei Jiang, Sparsh Mittal and Wujie Wen


3) Design Space Exploration of TAGE Branch Predictor with Ultra-Small RAM

Chaobing Zhou, Libo Huang, Zhisheng Li, Tan Zhang and Qiang Dou


4) A Power Efficient Architecture with Optimized Parallel Memory Accessing for Feature Generation

Peng Ouyang, Shouyi Yin, Chunxiao Xing, Leibo Liu and Shaojun Wei


5) Design of Approximate High-Radix Dividers by Inexact Binary Signed-Digit Addition

Fabrizio Lombardi, Linbin Chen, Weiqiang Liu, Jie Han and Paolo Montuschi


Special Sessions

Specal Session 1:

Low Power Computing based on Non-Volatile Memories
Advanced Low Power Spintronic Memories beyond STT-MRAM by Wang Kang, Zhaohao Wang, He Zhang, Sai Li, Youguang Zhang and Weisheng Zhao
Exploiting Non-Volatility for Information Processing by Robert Perricone, Li Tang, X. Sharon Hu and Michael Niemier
Neuromorphic Computing Based on Resistive RAM by Zixuan Chen, Huaqiang Wu, Bin Gao, Peng Yao, Xinyi Li and He Qian
Implications of the Use of Magnetic Tunnel Junctions as Synapses in Neuromorphic Systems by Adrien F. Vincent, Nicolas Locatelli, Qifan Wu and Damien Querlioz

Special Session 2:

Three-Dimensional Integrated Circuit (3D IC) Security
Security Threats and Countermeasures in Three-Dimensional Integrated Circuits by Jaya Dofe, Peng Gu, Dylan Stow, Qiaoyan Yu, Eren Kursun and Yuan Xie
Impact of Power Distribution Network on Power Analysis Attacks in Three-Dimensional Integrated Circuits by Jaya Dofe, Zhiming Zhang, Qiaoyan Yu, Chen Yan and Emre Salman
The Need for Declarative Properties in Digital IC Security by Mohamed El Massad, Frank Imeson, Siddharth Garg and Mahesh Tripunitara
Securing Split Manufactured ICs with Wire Lifting Obfuscated Built-In Self-Authentication by Qihang Shi, Kan Xiao, Domenic Forte and Mark Tehranipoor

Special Session 3:

Logic Obfuscation for IoT Security: A New Arms Race?
An Empirical Study on Gate Camouflaging Methods Against Circuit Partition Attack by Xueyan Wang, Qiang Zhou, Yici Cai and Gang Qu
What to Lock? Functional and Parametric Locking by Muhammad Yasin, Abhrajit Sengupta, Benjamin Carrion Schafer, Yiorgos Makris, Ozgur Sinanoglu and Jeyavijayan Rajendran
Circuit Obfuscation and Oracle-guided Attacks: Who Can Prevail?, by Kaveh Shamsi*, Meng Li**, Travis Meade*, Zheng Zhao**, David Z. Pan**, and Yier Jin*, * University of Central Florida and ** University of Texas at Austin
Comparative Analysis of Hardware Obfuscation for IP Protection , by Sarah Amir, Bicky Shakya, Domenic Forte, Mark Tehranipoor, and Swarup Bhunia, University of Florida

Special Session 4:

Efficient IoT Systems: The Power of Heterogenous Integration
Efficient and Secure On-Chip Reconfigurable Power Delivery for IoT Devices by Selcuk Kose
Design Space Modeling and Simulation for Physically Constrained 3D CPUs by Caleb Serafy, Zhiyuan Yang and Ankur Srivastava
Automated Design of Stable Power Delivery Systems for Heterogeneous IoT Systems by Inna Partin-Vaisband
Work Load Scheduling For Multi Core Systems With Under-Provisioned Power Delivery by Divya Pathak, Houman Homayoun and Ioannis Savidis

Poster Sessions

Poster Session I


CAD, VLSI Design, VLSI Circuits and Power Aware Design


A maze routing-based algorithm for ML-OARST with pre-selecting and ripping up and re-building Steiner points

Kuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li and Rung-Bin Lin.


An Integrated Optimization Framework for Partitioning, Scheduling and Floorplanning on Partially Dynamically Reconfigurable FPGAs

Xiaodong Xu, Qi Xu, Jinglei Huang and Song Chen


Communication-aware Partitioning for Energy Optimization of Large FPGA Designs

Kalindu Herath, Alok Prakash, Jiang Guiyuan and Thambipillai Srikanthan


Combined Centralized and Distributed Connection Allocation in Large TDM Circuit Switching NoCs

Yong Chen, Emil Matus and Gerhard Fettweis


Random Forest Architectures on FPGA for Multiple Applications

Xiang Lin, Shawn Blanton and Donald Thomas


Exploring Heterogeneous-ISA Core Architectures for High-Performance and Energy-Efficient Mobile SoCs

Wooseok Lee, Dam Sunwoo, Christopher D. Emmons, Andreas Gerstlauer and Lizy John


An FPGA Coarse Grained Intermediate Fabric for Regular Expression Search

Thomas Luinaud, Pierre Langlois and Yvon Savaria


Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems

Huimei Cheng, Ji Li, Jeffrey Draper, Shahin Nazarian and Yanzhi Wang


Energy Savings and Performance Improvement in Subthreshold Using Adaptive Body Bias

Rajsaktish Sankaranarayanan and Matthew R. Guthaus


Low voltage stochastic flash ADC with front-end of inverter-based comparative unit

Xuncheng Zou, Bo Liu and Shigetoshi Nakatake


An Energy Combiner Design for Multiple Microbial Energy Harvesting Sources

Ridvan Umaz and Lei Wang




Poster Session II


Testing/Reliability/Fault-Tolerance, Biochips and Biological Systems, Emerging Computing & Post-CMOS Technologies, Hardware Security


Throughput Optimization for Lifetime Budgeting in Many Core Systems

Liang Wang, Xiaohang Wang, Ho-Fung Leung and Terrence Mak


A Test Pattern Quality Metric for Diagnosis of Multiple Stuck-at and Transition faults

Sarmad Tanwir, Michael Hsiao and Loganathan Lingappan


Switched Capacitor and Infinite Impulse Response Summation For A Quarter-Rate DFE With 4Gb/s Data Rate

Gyunam Jeon and Yong-Bin Kim


Reducing Microfluidic Very Large Scale Integration (mVLSI) Chip Area by Seam Carving

Brian Crites, Karen Kong and Philip Brisk


LUTOSAP: Lookup-Table-Based Online Sample Preparation in Microfluidic Biochips

Lingxuan Shao, Yibin Yang, Hailong Yao and Tsung-Yi Ho



ProACt: A Processor for High Performance On-demand Approximate Computing

Arun Chandrasekharan, Daniel Große, and Rolf Drechsler

Softmax Regression Design for Stochastic Computing Based Deep Convolutional Neural Networks

Zihao Yuan, Ji Li, Zhe Li, Caiwen Ding, Ao Ren, Bo Yuan, Qinru Qiu, Jeffrey Draper and Yanzhi Wang,


Computing Polynomials with Positive Coefficients using Stochastic Logic by Double-NAND Expansion

Sayed Ahmad Salehi, Yin Liu, Marc Riedel and Keshab Parhi


On the Role of Sequential Circuits in Stochastic Computing

Pai-Shun Ting and John Hayes


Circuit Techniques for Online Learning of Memristive Synapses in CMOS-Memristor Neuromorphic Systems

Sagarvarma Sayyaparaju, Gangotree Chakma, Sherif Amer and Garrett S. Rose



Mitigating Control Flow Attacks in Embedded Systems with Novel Built-in Secure Register Bank

Sean Kramer, Zhiming Zhang, Jaya Dofe and Qiaoyan Yu


Using Security Invariant to Verify Confidentiality in Hardware Design

Shuyu Kong, Yuanqi Shen and Hai Zhou


Leveraging All-Spin Logic to Improve Hardware Security

Qutaiba Alasad, Jiann Yuan and Deliang Fan


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