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Program
Keynote 1: Re-thinking Computing with Neuro-Inspired Learning: Algorithms, Architecture, & Devices
Kaushik Roy
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Keynote 2: Evolving Trust for High Consequence Microelectronics
Vivian Kammler
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Keynote 3: An Air Force Perspective on the Application of Machine Learning for Microelectronics Design and Security
Len Orlando
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Keynote 4: Tuning Memory Fault Tolerance on the Edge
Alex Jones
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Technical Session 1A
Tuesday
June 22
10:30 - 12:00
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Tech Session 1A: VLSI for Machine Learning and Artificial Intelligence I
Co-Chair: Caiwen Ding
Co-Chair: Tao Liu
MT-DLA: An Efficient Multi-Task Deep Learning Accelerator Design
Mengdi Wang, Bing Li, Ying Wang, Cheng Liu, Xiaohan Ma, Xiandong Zhao and Lei Zhang
(Best Paper Award Candidate)
Bitwise Neural Network Acceleration using Silicon Photonics
Kyle Shiflett, Avinash Karanth, Ahmed Louri and Razvan Bunescu
Re2PIM: A Reconfigurable ReRAM-based PIM Design for Variable-sized Vector-Matrix Multiplication
Yilong Zhao, Zhezhi He, Naifeng Jing Jing, Xiaoyao Liang and Li Jiang
Tenet: A Neural Network Model Extraction Attack in Multi-core Architecture
Chengsi Gao, Bing Li, Ying Wang, Weiwei Chen and Lei Zhang
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Technical Session 1B
Tuesday
June 22
10:30 - 12:00
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Tech Session 1B: Computer-Aided Design (CAD) I
Chair: Hamed Tabkhivayghan
LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis
Muhammad Awais, Hassan Ghasemzadeh Mohammadi and Marco Platzner
EPEX: Processor Verification by Equivalent Program Execution
Lucas Klemmer and Daniel Grosse
IRONMAN: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning
Nan Wu, Yuan Xie and Cong Hao
(Best Paper Candidate)
SFP: Smart File-Aware Prefetching for Flash based Storage Systems
Han Wang, Longfei Luo, Liang Shi, Changlong Li, Chun Jason Xue, Qingfeng Zhuge and Edwin Sha
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Technical Session 2A
Tuesday
June 22
1:00 - 2:30
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Tech Session 2A: Emerging Computing & Post-CMOS Technologies
Co-Chair: Bing Li
Co-Chair: Georgios Sirakoulis
Equivalence Checking for Superconducting RSFQ Logic Circuits
Rongliang Fu, Junying Huang and Zhimin Zhang
(Best Paper Candidate)
CAMeleon: Reconfigurable B(T)CAM in Computational RAM
Zamshed Chowdhury, Salonik Resch, Hüsrev Cılasun, Zhengyang Zhao, Masoud Zabihi, Sachin S. Sapatnekar, Jian-Ping Wang and Ulya Karpuzcu
A Logarithmic Floating-Point Multiplier for the Efficient Training of Neural Networks
Zijing Niu, Honglan Jiang, Saeed Ansari, Bruce Cockburn, Leibo Liu and Jie Han
Eliminating Iterations of Iterative Methods: Solving Large-Scale Sparse Linear System in O(1) with RRAM-based In-Memory Accelerator
Tao Song, Xiaoming Chen and Yinhe Han
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Technical Session 2B
Tuesday
June 22
1:00 - 2:30
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Tech Session 2B: Hardware Security I
Chair: Satwik Patniak
On the Vulnerability of Hardware Masking in Practical Implementations
Haotian Dai and Selcuk Kose
The Modeling Attack and Security Enhancement of the XbarPUF with both Column Swapping and XORing
Yongliang Chen, Xiaole Cui, Wenqiang Ye and Xiaoxin Cui
APUF-BNN: An Automated Framework for Efficient Combinational Logic Based Implementation of Arbiter PUF through Binarized Neural Network
Pranesh Santikellur, Rijoy Mukherjee and Rajat Subhra Chakraborty
(Best Paper Candidate)
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Technical Session 3A
Wednesday
June 23
10:00 - 11:30
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Tech Session 3A: VLSI Design
Chair: Edison (Zhengyu) Chen
Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMs
Bobby Bose and Ishan Thakkar
(Best Paper Candidate)
Design of a Low-Overhead Random Number Generator Using CMOS-based Cascaded Chaotic Maps
Partha Sarathi Paul, Maisha Sadia, Md Razuan Hossain, Barry Muldrey and Md Sakib Hasan
CNN-DMA: A Predictable and Scalable Direct Memory Access Engine for Convolutional Neural Network with Sliding-window Filtering
Zheng Wang, Zhuo Wang, Jian Liao, Chao Chen, Weiguang Chen, Wenxuan Chen, Ming Lei, Bo Dong, Rui Chen, Yongkui Yang and Zhibin Yu
Improving Lifetime of Non-Volatile Memory Caches by Logical Partitioning
S Sivakumar, T M Abdul Khader and John Jose
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Technical Session 3B
Wednesday
June 23
10:00 - 11:30
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Tech Session 3B: Computer-Aided Design (CAD) II
Chair: Hamed Tabkhivayghan
Relaxed placement: minimizing shift operations for Racetrack Memory in hybrid SPM
Rui Xu, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Liang Shi, Shouzhen Gu and Yan Hou
Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design
Md Arafat Kabir, Dusan Petranovic and Yarui Peng
Concentration Gradients Enhancement of Christmas-Tree Structure Based on a Look-Up Table
Wei Zhang, Yongxiao Zhou, Tsung-Yi Ho and Hailong Yao
A Composable Glitch-Aware Delay Model
Jürgen Maier, Daniel Öhlinger, Ulrich Schmid, Matthias Függer and Thomas Nowak
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Technical Session 5B
Wednesday
June 23
2:30 - 4:00
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Tech Session 5B: VLSI for Machine Learning and Artificial Intelligence II
Co-Chair: Tau Liu
Co-Chair: Caiwen Ding
RECOIN: A Low-Power Processing-in-ReRAM Architecture for Deformable Convolution
Cheng Chu, Fan Chen, Dawen Xu and Ying Wang
Computing Utilization Enhancement for Chiplet-based Homogeneous Processing-in-Memory Deep Learning Processors
Bo Jiao, Haozhe Zhu, Jinshan Zhang, Shunli Wang, Xiaoyang Kang, Lihua Zhang, Mingyu Wang and Chixiao Chen
DeepDive: An Integrative Algorithm/Architecture Co-Design for Deep Separable Convolutional Neural Networks
Mohammadreza Baharani, Ushma Sunil, Kaustubh Manohar, Steven Furgurson and Hamed Tabkhi
IM3A: Boosting Deep Neural Network Efficiency via In-Memory Addressing-Assisted Acceleration
Fangxin Liu, Wenbo Zhao, Zongwu Wang, Tao Yang and Li Jiang
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Technical Session 6B
Thursday
June 24
10:00 - 11:00
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Tech Session 6B: Testing, Reliability, Fault-Tolerance
Co-Chair: Hussam Amrouch
Co-Chair: Wenjing Rao
A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments
Aibin Yan, Aoran Cao, Zhengzheng Fan, Zhelong Xu, Tianming Ni, Patrick Girard and Xiaoqing Wen
Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch design for Reliable Circuits
Neha Gupta, Nikhil Agrawal, Narendra Singh Dhakad, Ambika Prasad Shah, Santosh Kumar Vishvakarma and Patrick Girard
Tolerating Stuck-at Fault and Variation in Resistive Edge Inference Engine via Weight Mapping
Yu Ma, Linfeng Zheng and Pingqiang Zhou
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Technical Session 7B
Thursday
June 24
1:00 - 2:00
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Tech Session 7B: VLSI Circuits and Power Aware Design
Co-Chair: Zhuwei Qin
Co-Chair: Chenchen Liu
Unlocking Approximations through Selective Source Code Transformations
Prattay Chowdhury and Benjamin Carrion Schafer
Machine Learning Based Acceleration Method for Ordered Escape Routing
Zhiyang Chen, Weiqing Ji, Yihao Peng, Datao Chen, Mingyu Liu and Hailong Yao
(Best Paper Candidate)
Novel Approximate Multiplier Designs for Edge Detection Application
Yashaswi Mannepalli, Viraj Bharadwaj Korede and Madhav Rao
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Technical Session 8B
Thursday
June 24
2:00 - 3:30
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Tech Session 8B: Hardware Security II
Co-Chair: Soheil Mobarakeh
Co-Chair: Satwik Patniak
IVcache: Defending Cache Side Channel Attacks via Invisible Accesses
Yanan Guo, Youtao Zhang, Andrew Zigerelli and Jun Yang
Hardware Secure Execution and Simulation Model Correlation using IFT on RISC-V
Geraldine Shirley Nicholas, Bhavin Thakar and Fareena Saqib
Assessing DPA and CPA Attack Resilience of Logic Locking Techniques
Zhiming Zhang, Ivan Miketic, Emre Salman and Qiaoyan Yu
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Technical Session 9A
Friday
June 25
11:00 - 12:30
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Tech Session 9A: Microelectronic Systems Education
Co-Chair: Tina Hudson
Co-Chair: Mark Johnson
Socially-Distant Hands-On Labs for a Real-time Digital Signal Processing Course
Patrick Schaumont
(Best Paper Candidate)
ASIC Design Principal Course with Combination of Online-MOOC and Offline-Inexpensive FPGA Board
Zhixiong Di, Yongming Tang, Jiahua Lu and Zhaoyang Lv
Experiences with Remote Teaching an Embedded Systems Course
John Nestor
Discussion
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Special Session 4A
Wednesday
June 23
1:00 - 2:30
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Special Session 4A: AAA in ML: Machine Learning Algorithm/Architecture/Accelerator Co-Design
3U-EdgeAI: Ultra-Low Memory Training, Ultra-Low Bitwidth Quantization, and Ultra-Low Latency Acceleration
Yao Chen, Kaiqi Zhang, Zheng Zhang and Cong Hao
Accommodating Transformer onto FPGA: Coupling the Balanced Model Compression and FPGA-Implementation Optimization
Panjie Qi, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Yuhong Song, Hongwu Peng and Shaoyi Huang
HMC-TRAN: A Tensor-core Inspired Hierarchical Model Compression for Transformer-based DNNs on GPU
Shaoyi Huang, Shiyang Chen, Hongwu Peng, Daniel Manu, Zhenglun Kong, Geng Yuan, Lei Yang, Shusen Wang, Hang Liu and Caiwen Ding
Co-Exploration of Graph Neural Network and Network-on-Chip Design using AutoML
Daniel Manu, Shaoyi Huang, Caiwen Ding and Lei Yang
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Special Session 4B
Wednesday
June 23
1:00 - 2:30
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Special Session 4B: Secure Machine Learning with CAD
A Reinforced Learning Solution For Clock Skew Engineering to Reduce Peak Current and IR drop
Sayed Aresh Beheshti-Shirazi, Ashkan Vakil, Sai Manoj Pudukotai Dinakarrao, Ioannis Savidis, Houman Homayoun and Avesta Sasan
On the Adversarial Robustness of Quantized Neural Networks
Micah Gorsline, James Smith and Cory Merkel
Energy-Efficient and Adversarially Robust Machine Learning with Selective Dynamic Band Filtering
Neha Nagarkar, Khaled Khasawneh, Setareh Rafatirad, Avesta Sasan, Houman Homayoun and Sai Manoj Pudukotai Dinakarrao
Adversarial Attack Mitigation Approaches Using RRAM-Neuromorphic Architectures
Siddharth Barve, Sanket Shukla, Sai Manoj Pudukotai Dinakarrao and Rashmi Jha
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Special Session 5A
Wednesday
June 23
2:30 - 4:00
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Special Session 5A: New Trends in Hardware Security: Provisioning for Testing, Attack Resilience, and Lightweight Cryptography
The Curious Case of Trusted IC Provisioning in Untrusted Testing Facilities
Sandip Ray, Atul Prasad Deb Nath, Kshitij Raj and Swarup Bhunia
SAT Attack Resilience Measure for Access Restricted Circuits
Saran Phatharodom, Avesta Sasan and Ioannis Savidis
RANE: An Open-Source Formal De-obfuscation Attack for Reverse Engineering of Logic Encrypted Circuits
Shervin Roshanisefat, Hadi Mardani Kamali, Houman Homayoun and Avesta Sasan
Side-Channel Resistant Implementations of a Novel Lightweight Authenticated Cipher with Application to Hardware Security
Abubakr Abdulgadir, Sammy Lin, Farnoud Farahmand, Jens-Peter Kaps and Kris Gaj
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Special Session 8A
Thursday
June 24
2:00 - 3:30
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Special Session 8A: Towards Energy-efficient Machine Learning: Algorithm, Hardware and Computing Paradigm
Accelerating AI Applications using Analog In-Memory Computing: Challenges and Opportunities
Shravya Channamadhavuni, Sven Thijssen, Sumit Kumar Jha and Rickard Ewetz
A Comprehensive Analysis of Low-Impact Computations in Deep Learning Workloads
Hengyi Li, Zhichen Wang, Xuebin Yue, Wenwen Wang, Tomiyama Hiroyuki and Lin Meng
An Efficient Video Prediction Recurrent Network using Focal Loss and Decomposed Tensor Train for Imbalance Dataset
Mingshuo Liu, Kevin Han, Shiyi Luo, Mingze Pan, Mousam Hossain, Bo Yuan, Rondale F. DeMara and Yu Bai
Real-Time and Robust Hyperdimensional Classification
Alejandro Hernandez-Cano, Cheng Zhuo, Xunzhao Yin and Mohsen Imani
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Special Session 9B
Friday
June 25
11:00 - 12:30
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Special Session 9B: Emerging Security Topics in Neural Networks
Provably Accurate Memory Fault Detection Method for Deep Neural Networks
Omid Aramoon and Gang Qu
Unpaired Image-to-Image Translation Network for Semantic-based Face Adversarial Examples Generation
Jiliang Zhang and Junjie Hou
DNN Intellectual Property Protection: Taxonomy, Attacks and Evaluations (invited papers)
Mingfu Xue, Jian Wang and Weiqiang Liu
Security Enhancements for Approximate Machine Learning
He Li, Yaru Pang and Jiliang Zhang
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Special Session 10A
Friday
June 25
1:00 - 2:30
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Special Session 10A: Ferroelectric Technology: From Devices to Systems
Monte Carlo Variation Analysis of NCFET-based 6-T SRAM: Design Opportunities and Trade-offs
Shamiul Alam, Nazmul Amin, Sumeet Kumar Gupta and Ahmedullah Aziz
Overview of Ferroelectric Memory Devices and Reliability Aware Design Optimization
Shan Deng, Xiao Yi, Tongguang Yu, Zijian Zhao, Santosh Kurinec, Vijaykrishnan Narayanan and Kai Ni
Capacitive Content-Addressable Memory: A Highly Reliable and Scalable Approach to Energy-Efficient Parallel Pattern Matching Applications
Nuo Xiu, Yiming Chen, Guodong Yin, Xiaoyang Ma, Huazhong Yang, Sumitha George and Xueqing Li
Ferroelectric-based Accelerators for Computationally Hard Problems
Mohammad Khairul Bashar, Jaykumar Vaidya, RS Surya, Chonghan Lee, Feng Shi, Vijaykrishnan Narayanan and Nikhil Shukla
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Panel Session
Tuesday
June 22
2:30 - 4:00
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Panel: Security Challenges in SoC Design
Moderator: Ahmad-Reza Sadeghi
(1) Security verification challenges in large-scale SoC Designs (Arun Kanuparthi)
(2) What can go wrong: Tradeoffs between security and performance (Alric Althoff)
(3) HardFails 2.0: New lessons learned via cross-layer bugs (Jeyavijayan Rajendran)
Organizing The World’s Largest Hardware Security Competition: Challenges, Opportunities, and Lessons Learned
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Poster Session 6A
Thursday
June 24
10:00 - 11:00
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Poster Session 6A: Poster Session I
Chair: Qiaoyan Yu
Emerging Computing & Post-CMOS Technologies:
qMC: A Formal Model Checking Verification Framework For Superconducting Logic
Mustafa Munir, Aswin Gopikanna, Arash Fayyazi, Massoud Pedram and Shahin Nazarian
Processing-in-Memory Acceleration of MAC-based Applications Using Residue Number System: A Comparative Study
Shaahin Angizi, Arman Roohi, Mohammadreza Taheri amn Deliang Fan
A Hybrid Optical-Electrical Analog Deep Learning Accelerator Using Incoherent Optical Signals
Mingdai Yang, Mohammad Reza Jokar, Junyi Qiu, Qiuwen Lou, Yuming Liu, Aditi Udupa, Frederic T. Chong, John M. Dallesasse, Milton Feng, Lynford L. Goddard, X. Sharon Hu and Yanjing Li
Hardware Security:
Domain Isolation in FPGA-Accelerated Cloud and Data Center Applications
Joel Mandebi Mbongue, Sujan Kumar Saha and Christophe Bobda
MEDASec: Logic Encryption Scheme for Micro-electrode-dot-array Biochips IP Protection
Chen Dong, Lingqing Liu, Ximeng Liu, Huangda Liu and Sihuang Lian
VLSI Design:
Parallel Multipath Transmission for Burst Traffic Optimization in Point-to-Point NoCs
Hui Chen, Zihao Zhang, Peng Chen, Shien Zhu and Weichen Liu
Predictive Warp Scheduling for Efficient Execution in GPGPU
Abhinish Anand, Winnie Thomas, Suryakant Toraskar and Virendra Singh
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Poster Session 7A
Thursday
June 24
1:00 - 2:00
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Poster Session 7A: Poster Session II
Chair: Arman Roohi
Computer-Aided Design (CAD):
Minimally Invasive HW/SW Co-debug Live Visualization on Architecture Level
Pascal Pieper, Ralf Wimmer, Gerhard Angst and Rolf Drechsler
PALBBD: A Parallel ArcLength Method Using Bordered Block Diagonal Form for DC Analysis
Zhou Jin, Tian Feng, Yiru Duan, Xiao Wu, Minghou Cheng, Zhenya Zhou and Weifeng Liu
ALPINE: An Agile Processing-in-Memory Macro Compilation Framework
Jinshan Zhang, Bo Jiao, Yunzhengmao Wang, Haozhe Zhu, Lihua Zhang and Chixiao Chen
VLSI for Machine Learning and Artificial Intelligence:
Systolic-Array Deep-Learning Acceleration Exploring Pattern-Indexed Coordinate-Assisted Sparsity for Real-Time On-Device Speech Processing
Shiwei Liu, Zihao Zhao, Yanhong Wang, Qiaosha Zou, Yiyun Zhang and C. J. Richard Shi
Energy-Efficient Hybrid-RAM with Hybrid Bit-Serial based VMM Support
Chen Nie, Jie Lin, Huan Hu, Li Jiang, Xiaoyao Liang and Zhezhi He
MemOReL: A Memory-oriented Optimization Approach to Reinforcement Learning on FPGA-based Embedded Systems
Siva Satyendra Sahoo, Akhil Raj Baranwal, Salim Ullah and Akash Kumar
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GLSVLSI 2021 Webmaster
Yi-Chung Chen (ychen@tnstate.edu),
Tennessee State University.
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