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Program
Keynote 1: Smart Healthcare

Niraj Jha
Abstract:The Internet-of-Things (IoT) era promises hundreds of billions of devices or physical objects connected to the Internet. These objects include sensors, actuators, and processing elements that help us gather data, make intelligent decisions, and optimize processes. IoT is expected to have a potential economic impact of $3-6 trillion per year by 2025, with $1-2.5 trillion of this economic impact (its largest fraction) coming from smart healthcare applications. These healthcare applications will be enabled by various technologies, e.g., (i) neural network based detection and differential diagnosis using wearable medical sensors present in smartwatches and smartphones that will communicate with a health server to enable a physician to keep track of an individual’s health, (ii) image analytics, powered by accurate convolutional neural networks, with applications to radiology, pathology, ophthalmology, dermatology, cardiology, gastroenterology, etc., and (iii) personalized medical decision-making. However, many challenges remain in making this vision a reality. In this talk, we will explore how machine learning models employed at different layers of the healthcare hierarchy can begin to realize the above vision.
Bio: Niraj K. Jha received his B.Tech. degree in Electronics and Electrical Communication Engineering from Indian Institute of Technology, Kharagpur, India in 1981 and Ph.D. degree in Electrical Engineering from University of Illinois at Urbana-Champaign in 1985. He is a Professor of Electrical and Computer Engineering at Princeton University. He has served as an Associate Director for the Princeton Andlinger Center for Energy and the Environment. He is a Fellow of IEEE and ACM. He was given a Distinguished Alumnus Award by I.I.T., Kharagpur in 2014. He has co-authored five books among which are two textbooks that are being widely used around the world. He has served as the Editor-in-Chief of IEEE Transactions on VLSI Systems and on the editorial boards of several other IEEE Transactions. He is an author or co-author of more than 470 papers among which are 15 award-winning papers. His research interests include algorithms and architectures for machine learning, with applications to smart healthcare.
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Keynote 2: Closing the Gap between Quantum Algorithms and Machines with Hardware-Software Co-Design

Fred Chong
Abstract: Quantum computing is at an inflection point, where 127-qubit machines are deployed, and 1000-qubit machines are only a few years away.These machines have the potential to fundamentally change our concept of what is computable and demonstrate practical applications in areas such as quantum chemistry, optimization, and quantum simulation.
Yet a significant resource gap remains between practical quantum algorithms and real machines. A promising approach to closing this gap is to design software that is aware of the key physical properties of emerging quantum technologies. I will illustrate this approach with some of our recent work that focuses on techniques that break traditional abstractions and inform hardware design, including compiling programs directly to analog control pulses, computing with ternary quantum bits, 2.5D architectures for surface codes, and exploiting long-distance communication and tolerating atom loss in neutral-atom machines.
Bio: Fred Chong is the Seymour Goodman Professor in the Department of Computer Science at the University of Chicago and the Chief Scientist for Quantum Software at Infleqtion. He is also Lead Principal Investigator for the EPiQC Project (Enabling Practical-scale Quantum Computing), an NSF Expedition in Computing. Chong is a member of the National Quantum Advisory Committee (NQIAC) which provides advice to the President on the National Quantum Initiative Program. In 2020, he co-founded Super.tech, a quantum software company, which was acquired by Infleqtion (formerly ColdQuanta) in 2022. Chong received his Ph.D. from MIT in 1996 and was a faculty member and Chancellor's fellow at UC Davis from 1997-2005. He was also a Professor of Computer Science, Director of Computer Engineering, and Director of the Greenscale Center for Energy-Efficient Computing at UCSB from 2005-2015. He is a fellow of the IEEE and a recipient of the NSF CAREER award, the Intel Outstanding Researcher Award, and 13 best paper awards.
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Keynote 3: Microelectronics Security in CHIPS Era

Mark M. Tehranipoor
Abstract: The CHIPS Act has brought much needed excitement for onshoring/reshoring the front-end and back-end fabrication test and facilities. However, much of the security concerns during the design of modern system on chips (SoCs) or system-in-package (SiPs) have little to do with onshoring. This talk will discuss challenges to securing silicon development lifecycle with CHIPS in place, offer solutions to engineers and practitioners, and present research challenges and opportunities for academics.
Bio: Mark M. Tehranipoor is currently the Intel Charles E. Young Preeminence Endowed Chair Professor and the Chair of the Department of Electrical and Computer Engineering (ECE) at the University of Florida. His current research projects include: hardware security and trust, supply chain security, IoT security, VLSI design, test and reliability. He has 21 patents, 18 books, and 500+ conference/journal publications. He is a recipient of 17 best paper awards and nominations, as well as the 2008 IEEE Computer Society (CS) Meritorious Service Award, the 2012 IEEE CS Outstanding Contribution, the 2009 NSF CAREER Award, and the 2014 AFOSR MURI award. He received the 2020 University of Florida Innovation of the year as well as teacher/scholar of the year awards. He co-founded the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE). He serves on the program committee of more than a dozen leading conferences and workshops. He has also served as Program and General Chair of a number of IEEE and ACM sponsored conferences and workshops (HOST, ITC, DFT, D3T, DBT, NATW, and more). He is currently serving as a founding EIC for Journal on Hardware and Systems Security (HaSS) and served as Associate Editor for TC, JETTA, JOLPE, TODAES, IEEE D&T, TVLSI. He is currently serving as a founding director for Florida Institute for Cybersecurity Research (FICS) and a number of other centers with focus on microelectronics security. Dr. Tehranipoor is a Fellow of the IEEE, a Fellow of the ACM, a Fellow of the National Academy of Inventors (NAI), a Golden Core Member of IEEE CS, and Member of ACM SIGDA.
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Keynote 4: Hardware Security from the Information Perspective

Gang Qu
Abstract: Hardware security has received a lot of attention since 1996. This keynote provides a comprehensive view of the fundamental problems in hardware security to help integrated circuit (IC) designers and security researchers understand the security vulnerabilities in microelectronics supply chain, the available mitigations, the challenges and research opportunities. We consider hardware security as the study and implementation of protection for circuit design and fabrication, data storage and processing, as well as systems and sub-systems built on hardware. Based on this definition, key problems in hardware security can be categorized as intellectual property (IP) protection, secure storage and execution, and hardware security primitives. We present these problems and the corresponding solutions from a novel perspective of information battle between the attackers and designers where three types of information are involved: data collected, processed, and stored by the hardware; information hidden in the design as watermark, fingerprint, and Trojans; as well as chip fabrication variations and other physical features that can be extracted and utilized. Open problems and potential research directions will also be analyzed under this unified framework of information battle.
Bio: Dr. Gang Qu is a professor in the Department of Electrical and Computer Engineering at the University of Maryland, College Park. He has worked extensively in the areas of hardware security and low power design. He has made significant contribution in building the hardware security and trust community. Notably, he was an individual member of the VSIA intellectual property protection (IPP) development working group (2001) and contributed to VSIA’s IPP standards; he published the first book (2003) on hardware security, Intellectual Property Protection in VLSI Designs: Theory and Practice, based on his Ph.D. dissertation (2000); he developed a MOOC of hardware security on Coursera (2014); he co-founded the AsianHOST symposium (2016) and the IEEE CEDA hardware security and trust technique committee (HSTTC, 2020). Since October 2021, he has been working as a program director in the NSF Secure and Trustworthy Cyberspace (SaTC) program. He is a fellow of IEEE.
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Keynote 5: 20 Years After: New Thermal Challenges in Circuit Design and Architecture

Mircea Stan
Abstract: This keynote will offer future thermal research directions from the perspective of HotSpot, the most widely used open-source thermal modeling tool. HotSpot is 20 years old now (incidentally, there are also exactly 20 years since the keynote speaker was general chair for GLSVLSI 2003). The HotSpot original contributions were to recognize the need for thermal models to be "physical" in order to explore both spatial and temporal thermal variations and for the thermal tools to be compatible with the available design tools infrastructure. The keynote speaker is a circuit designer at heart and this influenced the original HotSpot thermal model: the model was based on a widely known electrical analogy for heat transfer that can be used to transform a complex 3D thermal model into a simpler thermal circuit with thermal resistances and thermal capacitances then solved using circuit solvers. Since the original development of HotSpot one of the significant changes has been the move to 3DIC and chiplets for which new cooling methods may be needed, particularly microfluidic cooling. Interestingly, as there is an electrical analogy of heat flow (power is analogous to electrical current, temperature is analogous to voltage, etc.), there is a similar analogy for fluid flow in which volumetric flow is analogous to electrical current and pressure is analogous to voltage. Thus one can build a circuit to model the microfluidic flow in addition to the conventional electrical circuit that represents the IC functionality and the thermal circuit that models heat flow. These three types of circuits are now part of the newest HotSpot 7.0 release. There are many needs for future thermal research, including the need for floorplans to be 2.5D and 3D floorplans, the need to model spatial variations and anisotropy due to fluidics, BEOL, TSV and bumps distribution, the need for composable thermal models with different trade-offs between accuracy and performance and the need for the architecture tools to become compatible with conventional EDA tools for validating post-RTL and post-P&R designs.
Bio: Mircea R. Stan is teaching and doing research in the areas of AI hardware, Processing in Memory, Cyber-Physical Systems, Computational RFID, spintronics, and nanoelectronics. Since 1996 he has been with the ECE Department at UVa, where he is now the Virginia Microelectronics Consortium (VMEC) endowed chair and Director of Computer Engineering. He received the 2018 Influential ISCA Paper Award for the 2003 best paper “Temperature-aware microarchitecture”. He is Editor-in-Chief for the IEEE TVLSI and was general chair for GLSVLSI 2003. Prof. Stan is a fellow of the IEEE.
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Invited Talk: Graph States and the Challenges for Efficient Quantum Circuit Compilation

Alexandru Paler
Abstract: Graphs can be used as a diagrammatic representation of entangled states: vertices represent qubits, and edges are the entangling gates performed between the qubits. Arbitrary quantum circuits can be compiled into a fault-tolerant gate set, and the resulting circuit can be reformulated as a graph state. Such graphs can be manipulated by local operations (single qubit/vertex gates) such that edges are added and removed in a well defined manner during a process called local complementation. The latter might have interesting applications for the optimisation of (fault-tolerant) quantum circuits, quantum communication networks and in general whenever, either: a) there is a need to minimize the number of edges (entangling gates) without affecting the functionality of the state, or b) the state has to be embedded into a quantum hardware architecture that has a different connectivity. This talk is partially based on the work from https://arxiv.org/abs/2209.07345.
Bio: Alexandru Paler is an assistant professor at Aalto University, Espoo, Finland. His research interests are on the aspects of fault-tolerant quantum computation, especially wrt surface code architectures: compilers, optimization methods and decoder implementations. He co-authored one of the first papers related to NISQ compilation for IBM computers and recently co-developed methods on how to use surface codes on restricted architectures or non-standard way. He is leading the quantum algorithms and software research group at Aalto University, and is the PI of two projects in the DARPA Quantum Benchmarking programme, in the QuantERA EQUIP project, and some national projects.
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Technical Session 1A
Monday
June 5
10:15 - 11:15
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Technical Session 1A: VLSI for Machine Learning and Artificial Intelligence I
Chairs: Ramtin Zand, Kanad Basu
IMA-GNN: In-Memory Acceleration of Centralized and Decentralized Graph Neural Networks at the Edge
(Best Paper Candidate)
Mehrdad Morsali, Mahmoud Nazzal, Abdallah Khreishah and Shaahin Angizi
Low Cost Multiple-Precision Multiplication Unit Design for Deep Learning
Jing Zhang, Libo Huang, Hongbing Tan, Ling Yang, Zhong Zheng and Qianming Yang
TRON: Transformer Neural Network Acceleration with Non-Coherent Silicon Photonics
Salma Afifi, Febin Sunny, Mahdi Nikdast and Sudeep Pasricha
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Technical Session 1B
Monday
June 5
10:15 - 11:15
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Technical Session 1B: VLSI Circuits and Design I
Chairs: Michael Zuzak, Mohammed Alawad
PEPA: Performance Enhancement of Embedded Processors through HW Accelerator Resource Sharing
Qilin Si and Benjamin Carrion Schafer
Optimize the TX Architecture of RDMA NIC for Performance Isolation in the Cloud Environment
Yunkun Liao, Jingya Wu, Wenyan Lu, Xiaowei Li and Guihai Yan
KPU-SQL: Kernel Processing Unit for High-Performance SQL Acceleration
(Best Paper Candidate)
Hao Kong, Haishuang Fan, Jingya Wu, Liyun Cheng, Yan Chen, Wenyan Lu, Guihai Yan and Xiaowei Li
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Technical Session 2A
Monday
June 5
11:25 - 12:25
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Technical Session 2A: Hardware Security I
Chairs: Ujjwal Guin, Soheil Salehi
SCRAMBLE-CFI: Mitigating Fault-Induced Control-Flow Attacks on OpenTitan
(Best Paper Candidate)
Pascal Nasahl and Stefan Mangard
HT-EMIS: A Deep Learning Tool for Hardware Trojan Detection and Identification through Runtime EM Side-Channels
Hanqiu Wang, Max Panoff, Shuo Wang and Domenic Forte
Exploring Remote Power Attacks Targeting Parallel Data Encryption on Multi-Tenant FPGAs
Yankun Zhu, Jindong Zhou and Pingqiang Zhou
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Technical Session 2B
Monday
June 5
11:25 - 12:25
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Technical Session 2B: VLSI Circuits and Design II
Chairs: Shaahin Angizi, Amit Degada
Stochastically Pruning Large Language Models Using Sparsity Regularization and Compressive Sensing
Mohammed Alawad
M2VT: a Multi-output Encoder Accelerator for Multiple-Way Video Transcoding
Haishuang Fan, Jingya Wu, Wenyan Lu, Guihai Yan and Xiaowei Li
TPNoC: An Efficient Topology Reconfigurable NoC Generator
Jiangnan Yu, Fan Yang, Xiaoling Yi, Chixiao Chen, Jun Tao, Dong Xu, Xiankui Xiong and Haitao Yang
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Technical Session 3A
Tuesday
June 6
10:20 - 11:40
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Technical Session 3A: IoT and Smart Systems
Chairs: Shaahin Angizi, Kaveh Shamsi
PUFchain 4.0: Integrating PUF-based TPM in Distributed Ledger for Security-by-Design of IoT
(Best Paper Candidate)
Venkata Karthik Vishnu Vardhan Bathalapalli, Saraju Mohanty, Elias Kougianos, Vasanth Iyer and Bibhudutta Rout
Precision and Performance-Aware Voltage Scaling in DNN Accelerators
Mallika Rathore, Peter Milder and Emre Salman
Facial Expression Recognition at the Edge: CPU vs GPU vs VPU vs TPU
Mohammadreza Mohammadi, Heath Smith, Lareb Khan and Ramtin Zand
Fortified-Edge: Secure PUF Certificate Authentication Mechanism for Edge Data Centers in Collaborative Edge Computing
Seema Aarella, Deepak Puthal, Saraju Mohanty and Elias Kougianos
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Technical Session 3B
Tuesday
June 6
10:20 - 11:40
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Technical Session 3B: Emerging Computing and Post-CMOS Technologies I
Chairs: Maryam Parsa, Mohamed I. Ibrahim
SOAER: Self-Obstacle Avoiding Escape Routing for Paper-Based Digital Microfluidic Biochips
Weiqing Ji, Xingcheng Yao, Hailong Yao, Tsung-Yi Ho and Xia Yin
Reconfigurable Mapping Algorithm based Stuck-At-Fault Mitigation in Neuromorphic Computing Systems
Md. Oli-Uz-Zaman, Saleh Ahmad Khan, William Oswald, Zhiheng Liao and Jinhui Wang
Digital LIF Neuron for CTT-Based Neuromorphic Systems
Okyanus Gumus, Mousa Karimi and Boris Vaisband
Bit-Stream Processing with No Bit-Stream: Efficient Software Simulation of Stochastic Vision Machines
(Best Paper Candidate)
Sercan Aygün, M. Hassan Najafi, Mohsen Imani and Ece Olcay Gunes
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Technical Session 4A
Tuesday
June 6
1:25 - 2:45
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Technical Session 4A: Testing, Reliability, Fault-Tolerance
Chairs: Ujjwal Guin, Jinhui Wang
RFAM: RESET-Failure-Aware-Model for HfO2-based Memristor to Enhance the Reliability of Neuromorphic Design
Hritom Das, Manu Rathore, Rocco Febbo, Maximilian Liehr, Nathaniel Cady and Garrett S. Rose
SiFI-AI: A Fast and Flexible RTL Fault Simulation Framework Tailored for AI Models and Accelerators
Julian Hoefer, Fabian Kempf, Tim Hotfilter, Fabian Kreß, Tanja Harbaum and Juergen Becker
Two Highly Reliable and High-Speed SRAM Cells for Safety-Critical Applications
Aibin Yan, Yang Chang, Jing Xiang, Hao Luo, Jie Cui, Zhengfeng Huang, Tianming Ni and Xiaoqing Wen
FPGNN-ATPG: An Efficient Fault Parallel Automatic Test Pattern Generator
Yuyang Ye, Zonghui Wang, Zun Xue, Ziqi Wang, Yifei Gao, Hao Yan and Longxing Shi
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Technical Session 4B
Tuesday
June 6
1:25 - 2:45
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Technical Session 4B: Computer-Aided Design (CAD) I
Chairs: Emre Salman, Sunwoong "Sunny" Kim
More Efficient Accuracy-Ensured Waveform Compression for Circuit Simulation Supporting Asynchronous Waveforms
(Best Paper Candidate)
Lingjie Li, Wenjian Yu, Genhua Guo and Zhenya Zhou
DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network
Jhen-Gang Lin, Yu-Guang Chen, Yun-Wei Yang, Wei-Tse Hung, Cheng-Hong Tsai, De-Shiun Fu and Mango Chia-Tso Chao
Placement Legalization Amenable to Mixed-cell-height Standard Cells Integrating into State-of-the-art Commercial EDA Tool
Hwapyong Kim and Taewhan Kim
ADVICE: Automatic Design and Optimization of Behavioral Application Specific Processors
Qilin Si and Benjamin Carrion Schafer
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Technical Session 5A
Wendesday
June 7
10:15 - 11:35
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Technical Session 5A: VLSI for Machine Learning and Artificial Intelligence II
Chairs: Ramtin Zand, Sunwoong "Sunny" Kim
GAT-based Concentration Prediction for Random Microfluidic Mixers with Multiple Input Flow Rates
Weiqing Ji, Hailong Yao, Tsung-Yi Ho, Ulf Schlichtmann and Xia Yin
Exploring Architecture, Dataflow, and Sparsity for GCN Accelerators: A Holistic Framework
Lingxiang Yin, Jun Wang and Hao Zheng
SenTer: A Reconfigurable Processing-in-Sensor Architecture Enabling Efficient Ternary MLP
Sepehr Tabrizchi, Rebati Gaire, Shaahin Angizi and Arman Roohi
IMAC: A Pre-Multiplier and Integrated Reduction Based Multiply-And-Accumulate Unit
Bindu G Gowda, Prashanth H C and Madhav Rao
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Technical Session 5B
Wendesday
June 7
10:15 - 11:35
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Technical Session 5B: Emerging Computing and Post-CMOS Technologies II
Chairs: Rassul Bairamkulov, Edgard Munoz-Coreas
Reinforcement Learning based Reliability-Aware Module Placement in MEDA Digital Microfluidic Biochips
Debraj Kundu, Gadikoyila Satya Vamsi, Karnati Vivek Veman, Gurram Mahidhar and Sudip Roy
JRouter: A Multi-Terminal Hierarchical Length-Matching Router under Planar Manhattan Routing Model for RSFQ Circuits
Xinda Chen, Rongliang Fu, Junying Huang, Huawei Cao, Zhimin Zhang, Xiaochun Ye, Tsung-Yi Ho and Dongrui Fan
Ternary In-Memory Computing with Cryogenic Quantum Anomalous Hall Effect Memories
Arun Govindankutty, Shamiul Alam, Sanjay Das, Nagadastagiri Challapalle, Ahmedullah Aziz and Sumitha George
ATC: Approximate Temporal Coding for Efficient Implementations of Spiking Neural Networks
Ming Han, Ye Wang, Jian Dong, Heng Liu, Jin Wu and Gang Qu
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Technical Session 6A
Wednesday
June 7
12:50 - 2:10
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Technical Session 6A: Hardware Security II
Chairs: Amin Rezaei, Michael Zuzak
Fault Recovery from Multi-Tenant FPGA Voltage Attacks
Shayan Moini, Dhruv Kansagara, Daniel Holcomb and Russell Tessier
MAYAVI: A Cyber-Deception Hardware for Memory Load-Stores
Preet Derasari, Kailash Gogineni and Guru Venkataramani
On-Demand Device Authentication using Zero-Knowledge Proofs for Smart Systems
Yadi Zhong, Joshua Hovanes and Ujjwal Guin
TimingCamouflage+ Decamouflaged
Priya Mittu, Yuntao Liu and Ankur Srivastava
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Technical Session 6B
Wednesday
June 7
12:50 - 2:10
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Technical Session 6B: Computer-Aided Design (CAD) II
Chair: Rassul Bairamkulov
ESFO:Equality Saturation for FIRRTL Optimization
Pi Yan, Zou Hongji, Li Tun, Qu Wanxia and Wan Hai
TDAG: Tree-based Directed Acyclic Graph Partitioning for Quantum Circuits
Joseph Clark, Travis Humble and Himanshu Thapliyal
SPARK: A Scalable Partitioning and Routing Framework for Multi-FPGA Systems
Xinshi Zang, Martin D.F. Wong and Evangeline F.Y. Young
GUI-VP Kit: A RISC-V VP Meets Linux Graphics - Enabling Interactive Graphical Application Development
Manfred Schlaegl and Daniel Grosse
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Technical Session 7A
Wednesday
June 7
2:20 - 3:40
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Technical Session 7A: VLSI Circuits and Design III
Chair: Ujjwal Guin, Kaveh Shamsi
A Scalable Platform for Single-Snapshot Direction Of Arrival (DOA) Estimation in Massive MIMO Systems
Adou Sangbone Assoa, Ashwin Bhat, Sigang Ryu and Arijit Raychowdhury
ILAFD: Accuracy-Configurable Floating-Point Divider Using an Approximate Reciprocal and an Iterative Logarithmic Multiplier
James Oelund and Sunwoong Kim
Design of Energy Efficient Posit Multiplier
Aditya Anirudh Jonnalagadda, Anil Kumar Uppugunduru, Sreehari Veeramachaneni and Syed Ershad Ahmed
Ethics in Computing Education: Challenges and Experience with Embedded Ethics
Sudeep Pasricha
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Technical Session 7B
Wednesday
June 7
2:20 - 3:40
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Technical Session 7B: Emerging Computing and Post-CMOS Technologies III
Chair: Ramtin Zand, Ishan G Thakkar
IMAC-Sim: A Circuit-level Simulator for In-Memory Analog Computing Architectures
Md Hasibul Amin, Mohammed E. Elbtity and Ramtin Zand
Scalable Time-Domain Compute-in-Memory BNN Engine with 2.06 POPS/W Energy Efficiency for Edge-AI Devices
Jie Lou, Florian Freye, Christian Lanius and Tobias Gemmeke
CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators
Salim Ullah, Siva Satyendra Sahoo and Akash Kumar
A Machine Learning based Load Value Approximator guided by the Tightened Value Locality
Alain Aoun, Mahmoud Masadeh and Sofiene Tahar
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Special Session 1
Monday
June 5
3:20 – 4:40
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Special Session 1: Smart Healthcare Technologies
Chair: Rajdeep Kumar Nath
Towards Self-Supervised Learning of ECG Signal Representation for the Classification of Acute Stress Types
Rajdeep Kumar Nath, Jaakko Tervonen, Johanna Närväinen, Kati Pettersson and Jani Mäntyjärvi
OTFT based Biosensor for Detection of Breast Cancer Biomarker (C-erbB-2)
Sushil Kumar Jain and Amit Mahesh Joshi
hChain: Blockchain Based IoMT EHR National Data Sharing with Enhanced Security аnd Privacy Location-Based-Authentication
Musharraf Alruwaill, Saraju Mohanty and Elias Kougianos
CASD-OA: Context-Aware Stress Detection for Older Adults with Machine Learning and Cortisol Biomarke
Md. Saif Hassan Onim and Himanshu Thapliyal
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Special Session 2
Monday
June 5
3:20 - 4:40
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Special Session 2: Quantum from Circuits and Algorithms to Systems and Applications
Chairs: Robert Basmadijan, Edgard Munoz-Coreas
Search Space Reduction for Efficient Quantum Compilation
Amisha Srivastava, Chao Lu, Navnil Choudhury, Ayush Arunachalam and Kanad Basu
Scalable Hybrid CMOS-Diamond Quantum Magnetometers
Mohamed Ibrahim
Fingerprinting Quantum Computer Equipment
Jalil Morris, Anisul Abedin, Chuanqi Xu and Jakub Szefer
A logarithmic depth Quantum Carry-Lookahead Modulo (2n - 1) Adder
Bhaskar Gaur, Edgard Munoz-Coreas and Himanshu Thapliyal
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Special Session 3
Monday
June 5
3:20 - 4:40
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Special Session 3: Emerging Technologies in Neuromorphic Computing
Chairs: Catherine Schuman, Mohammed Alawad
Reliability Analysis of Memristive Reservoir Computing Architecture
Manu Rathore, Rocco Febbo, Adam Foshie, S. N. B. Tushar, Hritom Das and Garrett S. Rose
Hardware Accelerators for Spiking Neural Networks for Energy-Efficient Edge Computing
Abhishek Moitra, Ruokai Yin and Priyadarshini Panda
A Brain-inspired Approach for Malware Detection using Sub-semantic Hardware Features
Maryam Parsa, Khaled Khasawneh and Ihsen Alouani
A Cryogenic Artificial Synapse based on Superconducting Memristor
Md Mazharul Islam, Shamiul Alam, Md Shafayat Hossain and Ahmedullah Aziz
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Special Session 4
Tuesday
June 6
1:25 – 2:45
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Special Session 4: Machine Learning and Hardware Security: A Winning Combo!
Chairs: Amin Rezaei, Peter A Beerel
Island-based Random Dynamic Voltage Scaling vs ML-Enhanced Power Side-Channel Attacks
Dake Chen, Christine Goins, Maxwell Waugaman, Georgios Dimou and Peter Beerel
CoLA: Convolutional Neural Network Model for Secure Low Overhead Logic Locking Assignment
Yeganeh Aghamohammadi and Amin Rezaei
Enhancing Solver-based Generic Gate-Level Side-Channel Analysis with Machine-Learning
Kaveh Shamsi and Guangwei Zhao
Exploiting Logic Locking for a Neural Trojan Attack on Machine Learning Accelerators
Hongye Xu, Dongfang Liu, Cory Merkel and Michael Zuzak
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Special Session 5
Wednesday
June 7
10:15 – 11:35
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Special Session 5: Optical Computing for Emerging VLSI Systems
Chair: Mohamed I. Ibrahim
Design Space Exploration for PCM-based Photonic Memory
Amin Shafiee, Benoit Charbonnier, Sudeep Pasricha and Mahdi Nikdast
Cross-Layer Design for AI Acceleration with Non-Coherent Optical Computing
Febin Sunny, Mahdi Nikdast and Sudeep Pasricha
High-Speed and Energy-Efficient Non-Binary Computing with Polymorphic Electro-Optic Circuits and Architectures
Ishan Thakkar, Sairam Sri Vatsavai and Venkata Sai Praneeth Karempudi
Multi-Transverse-Mode Silicon Photonics for Quantum Computing
Kaveh Rahbardar Mojaver and Odile Liboiron-Ladouceur
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Special Session 6
Wednesday
June 7
12:50 – 2:10
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Special Session 6: Efficient In-Memory and In-Sensor Computing Platforms
Chair: Shaahin Angizi, Ishan G Thakkar
Heterogeneous Integration of In-Memory Analog Computing Architectures with Tensor Processing Units
Mohammed Elbtity, Brendan Reidy, Md Hasibul Amin and Ramtin Zand
Technology-Circuit-Algorithm Tri-Design for Processing-in-Pixel-in-Memory (P2M)
Md Abdullah-Al Kaiser, Gourav Datta, Sreetama Sarkar, Souvik Kundu, Zihan Yin, Manas Garg, Ajey Jacob, Peter Beerel and Akhilesh Jaiswal
Examining the Role and Limits of Batchnorm Optimization to Mitigate Diverse Hardware-noise in In-memory Computing
Abhiroop Bhattacharjee, Abhishek Moitra, Youngeun Kim, Yeshwanth Venkatesha and Priyadarshini Panda
Accelerating Low Bit-width Neural Networks at the Edge, PIM or FPGA: A Comparative Study
Nakul Kochar, Lucas Ekiert, Deniz Najafi, Deliang Fan and Shaahin Angizi
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Special Session 7
Wednesday
June 7
2:20 – 3:40
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Special Session 7: Machine Learning and Reconfigurability: Towards Sustainable Security
Chair: Soheil Salehi, Farimah Farahmandi
Metrics-to-Methods: Decisive Reverse Engineering Metrics for Resilient Logic Locking
Mohammad Sazadur Rahman, Kimia Zamiri Azar, Farimah Farahmandi and Hadi M Kamali
Machine Learning for Intrusion Detection: Stream Classification Guided by Clustering for Sustainable Security in IoT
Martin Manuel Lopez, Sicong Shao, Salim Hariri and Soheil Salehi
System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning
Kaniz Mishty and Mehdi Sadi
Prognosis of Aging-Induced Failure via Digital Sensors
Md Toufiq Hasan Anik, Hasin Ishraq Reefat, Jean-Luc Danger, Sylvain Guilley and Naghmeh Karimi
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Panel Session 1
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Panel Session 2
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Poster Session 1
Monday
June 5
4:40 - 6:10
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Poster Session 1
Chair: Lu Peng, Rajdeep Kumar Nath
VLSI Circuits and Design:
A Context-Switching/Dual-Context ROM Augmented RAM using Standard 8T SRAM
Md Abdullah-Al Kaiser, Edwin Tieu, Ajey Jacob and Akhilesh Jaiswal
MCSim: A Multi-Core Cache Simulator accelerated on a resource-constrained FPGA
Shivani Shah and Nanditha P Rao
Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect
Zhenlin Pei, Mahta Mayahinia, Hsiao-Hsuan Liu, Mehdi Tahoori, Francky Catthoor, Zsolt Tokei and Chenyun Pan
Design and Evaluation of Finite Field Multipliers using fast XNOR cells
Nitin Patwari, Anjul Srivastav, Mayank Kabra, Prashant Jonna and Madhav Rao
A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications
Aibin Yan, Shaojie Wei, Jinjun Zhang, Jie Cui, Jie Song, Tianming Ni, Patrick Girard and Xiaoqing Wen
RBGC: Repurpose the Buffer of Fixed Graphics Pipeline to Enhance GPU Cache
Haoyu Zhao, Longbing Zhang and Fuxin Zhang
VLSI for Machine Learning and Artificial Intelligence:
A Mixed-Signal Short-Term Plasticity Implementation for a Current-Controlled Memristive Synapse
Nishith Nirjhar Chakraborty, Hritom Das and Garrett Rose
XMG-GPPIC: Efficient and Robust General-Purpose Processing-in-Cache with XOR-Majority-Graph
Chen Nie, Xianjue Cai, Chenyang Lv, Chen Huang, Weikang Qian and Zhezhi He
SRAM-Based Processing-In-Memory Design with Kullback-Leibler Divergence-Based Dynamic Precision Quantization
Yanjun Li, Chunshan Zu, Bingqian Wang, Zhenhua Zhu, Yaojun Zhang, Ran Duan, Bing Li and Bonan Yan
Inter-Layer Hybrid Quantization Scheme for Hardware Friendly Implementation of Embedded Deep Neural Networks
Najmeh Nazari and Mostafa Ersali Salehi Nasab
RL-Ripper: A Framework for Global Routing Using Reinforcement Learning and Smart Net Ripping Techniques
Upma Gandhi, Erfan Aghaeekiasaraee, Ismail S. K. Bustany, Payam Mousavi, Matthew E. Taylor and Laleh Behjat
A Runtime-Reconfigurable Hardware Encoder for Spiking Neural Networks
Sk Hasibul Alam, Adam Foshie and Garrett Rose
FlutPIM: A Look-up Table-based Processing in Memory Architecture with Floating-point computation Support for Deep Learning Applications
Purab Ranjan Sutradhar, Sathwika Bavikadi, Mark Indovina, Sai Manoj Pudukotai Dinakarrao and Amlan Ganguly
Late Breaking Results:
Statistical Weight Refresh System for CTT-Based Synaptic Arrays
Samuel Dayo, Ataollah Saeed Monir, Mousa Karimi and Boris Vaisband
Lightweight Hierarchical Root-of-Trust Framework for CAN-based 3D Printing Security
Tyler Cultice, Joseph Clark and Himanshu Thapliyal
On Feasibility of Decision Trees for Edge Intelligence in Highly Constrained Internet-of-Things (IoT)
Raaga Sai Somesula, Rajeev Joshi and Dr. Srinivas Katkoori
A Scalable BFloat16 Dot-Product Architecture for Deep Learning
Jing Zhang, Huang Libo, Hongbing Tan, Zhong Zheng and Hui Guo
Confidence Counter Modelling for Value Predictor
Ling Yang, Libo Huang and Zhong Zheng
Unaligned Access Optimization with Request-based Mapping Scheme for Solid-state Drives
Minjun Li
Reconvergent Path-aware Simulation of Bit-stream Processing
Sercan Aygün, M. Hassan Najafi, Mohsen Imani and Ece O. Gunes
Radiation Hardened and Leakage Power Attack Resilient 12T SRAM Cell for Secure Nuclear Environments
Debabrata Mondal, Syed Farah Naz and Ambika Prasad Shah
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Poster Session 2
Tuesday
June 6
4:25 - 5:55
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Poster Session 2
Chair: Lu Peng, Rajdeep Kumar Nath
Computer-Aided Design:
CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems
Xinshi Zang, Lei Chen, Xing Li, Wilson W.K. Thong, Weihua Sheng, Evangeline F.Y. Young and Martin D.F. Wong
Hybrid-Row-Height Design Placement Legalization Considering Cell Variants
Syuan-Han Liang, Tsu-Ling Hsiung, Wai-Kei Mak and Ting-Chi Wang
An Efficient and Robust Algorithm for Common Path Pessimism Removal in Large Designs
Mengshi Gong, Jie Ma and Wenxin Yu
Efficient and Effective Digital Waveform Compression for Large-scale Logic Simulation of Integrated Circuit
Zhenyi Gao, Yuyang Xie and Wenjian Yu
A High-accurate Multi-objective Ensemble Exploration Framework for Design Space of CPU Microarchitecture
Duo Wang, Mingyu Yan, Yihan Teng, Dengke Han, Xiaochun Ye and Dongrui Fan
DrPIM: An Adaptive and Less-blocking Data Replication Framework for Processing-in-Memory Architecture
Sheng Xu, Hongyu Xue, Le Luo, Liang Yan and Xingqi Zou
A Macro Legalization Approach Considering Minimum Channel Spacing and Buffer Area Reservation Constraints
Chun-Wei Chiu, Yun-Kai Fang, Shao-Ting Chung and Ting-Chi Wang
Emerging Computing & Post-CMOS Technologies:
Stochastic Computing for Reliable Memristive In-Memory Computation
Mohsen Riahi Alam, M. Hassan Najafi, Nima Taherinejad, Mohsen Imani and Lu Peng
High-Density FeFET-based CAM Cell Design Via Multi-Dimensional Encoding
Hadi Noureddine, Omar Bekdache, Mohamad Al Tawil, Rouwaida Kanj, Ali Chehab, Ahmed Eltawil and Mohammed Fouda
Locate: Low-Power Viterbi Decoder Exploration using Approximate Adders
Rajat Bhattacharjya, Biswadip Maity and Nikil Dutt
Graph Neural Network Assisted Quantum Compilation for Qubit Allocation
Travis LeCompte, Fang Qi, Xu Yuan, Nian-Feng Tzeng, M. Hassan Najafi and Lu Peng
Compound Logic Gates for Pipeline Depth Minimization in Single Flux Quantum Integrated Systems
Rassul Bairamkulov and Giovanni De Micheli
Noise-Resilient and Reduced Depth Approximate Adders for NISQ Quantum Computing
Bhaskar Gaur, Travis Humble and Himanshu Thapliyal
Hardware Security:
SVP: Safe and Efficient Speculative Execution Mechanism through Value Prediction
Kaixuan Wang, Xinyu Qin, Zhuoyuan Yang, Weiliang He, Yifan Liu and Jun Han
Dynamic Gold Code-Based Chaotic Clock for Cryptographic Designs to Counter Power Analysis Attacks
Thai-Ha Tran, Anh-Tien Le, Trong-Thuc Hoang, Van-Phuc Hoang and Cong-Kha Pham
RAGA: Resource-Aware Tree-Splitting for High Performance Knuth-Yao-based Discrete Gaussian Sampling on FPGAs
Zachary J Ellis, Anupam Golder, Addison J Elliott and Arijit Raychowdhury
IoT and Smart Systems:
Efficient Off-Policy Reinforcement Learning via Brain-Inspired Computing
Yang Ni, Danny Abraham, Mariam Issa, Yeseong Kim, Pietro Mercati and Mohsen Imani
High-Throughput Edge Inference for BERT models via Neural Architecture Search and Pipeline
Hung-Yang Chang, Seyyed Hasan Mozafari, James Clark, Brett Meyer and Warren Gross
Enhancing the Security of Collaborative Deep Neural Networks: An Examination of the Effect of Low Pass Filters
Adewale Adeyemo and Syed Rafay Hasan
Design Space Exploration of Layer-Wise Mixed-Precision Quantization with Tightly Integrated Edge Inference Units
Xiaotian Zhao, Yimin Gao, Vaibhav Verma, Ruge Xu, Mircea Stan and Xinfei Guo
Testing, Reliability, Fault-Tolerance:
EBASA: Error Balanced Approximate Systolic Array Architecture Design
Sai Karthik Nandigama, Bindu G Gowda, Prashanth H C and Madhav Rao
Verilog-A Implementation of Generic Defect Templates for Analog Fault Injection
Nicola Dall'Ora, Sadia Azam, Enrico Fraccaroli, Renaud Gillon and Franco Fummi
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Panelists
Menon Vivek

Bio: Vivek Menon is the Mission Assurance Director in the Systems Engineering Directorate at the National Reconnaissance Office. He is responsible for the Microelectronics roadmap and strategy for NRO. His research interests are in microelectronics security, zero knowledge proofs, zero-trust architecture, and supply chain provenance. He is a Senior Member of IEEE and received his Ph.D. in Computer Engineering from Virginia Tech.
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Mark Tehranipoor

Bio: Mark M. Tehranipoor is currently the Intel Charles E. Young Preeminence Endowed Chair Professor and the Chair of the Department of Electrical and Computer Engineering (ECE) at the University of Florida. His current research projects include: hardware security and trust, supply chain security, IoT security, VLSI design, test and reliability. He has 21 patents, 18 books, and 500+ conference/journal publications. He is a recipient of 17 best paper awards and nominations, as well as the 2008 IEEE Computer Society (CS) Meritorious Service Award, the 2012 IEEE CS Outstanding Contribution, the 2009 NSF CAREER Award, and the 2014 AFOSR MURI award. He received the 2020 University of Florida Innovation of the year as well as teacher/scholar of the year awards. He co-founded the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE). He serves on the program committee of more than a dozen leading conferences and workshops. He has also served as Program and General Chair of a number of IEEE and ACM sponsored conferences and workshops (HOST, ITC, DFT, D3T, DBT, NATW, and more). He is currently serving as a founding EIC for Journal on Hardware and Systems Security (HaSS) and served as Associate Editor for TC, JETTA, JOLPE, TODAES, IEEE D&T, TVLSI. He is currently serving as a founding director for Florida Institute for Cybersecurity Research (FICS) and a number of other centers with focus on microelectronics security. Dr. Tehranipoor is a Fellow of the IEEE, a Fellow of the ACM, a Fellow of the National Academy of Inventors (NAI), a Golden Core Member of IEEE CS, and Member of ACM SIGDA.
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Anne Matsuura

Bio: Dr. Anne Matsuura is the Director of Quantum Applications & Architecture at Intel Labs. Her team focuses on creating algorithms and the system architecture for quantum computing systems Previously, she held positions as the Chief Scientist of the Optical Society (OSA) and the Chief Executive of the European Theoretical Spectroscopy Facility (ETSF). She has been a strategic investor in technology start-ups at In-Q-Tel, a funder of basic science at the Air Force Office of Scientific Research, and has experience as a science policymaker as a special assistant to the U.S. Deputy Under Secretary of Defense for Laboratories and Basic Science. Anne was the recipient of a Fulbright Scholarship to Japan and is an elected fellow of the OSA. Anne received her Ph.D. in physics from Stanford University.
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Fred Chong

Bio: Fred Chong is the Seymour Goodman Professor in the Department of Computer Science at the University of Chicago and the Chief Scientist for Quantum Software at Infleqtion. He is also Lead Principal Investigator for the EPiQC Project (Enabling Practical-scale Quantum Computing), an NSF Expedition in Computing. Chong is a member of the National Quantum Advisory Committee (NQIAC) which provides advice to the President on the National Quantum Initiative Program. In 2020, he co-founded Super.tech, a quantum software company, which was acquired by Infleqtion (formerly ColdQuanta) in 2022. Chong received his Ph.D. from MIT in 1996 and was a faculty member and Chancellor's fellow at UC Davis from 1997-2005. He was also a Professor of Computer Science, Director of Computer Engineering, and Director of the Greenscale Center for Energy-Efficient Computing at UCSB from 2005-2015. He is a fellow of the IEEE and a recipient of the NSF CAREER award, the Intel Outstanding Researcher Award, and 13 best paper awards.
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Gang Qu

Bio: Dr. Gang Qu is a professor in the Department of Electrical and Computer Engineering at the University of Maryland, College Park. He has worked extensively in the areas of hardware security and low power design. He has made significant contribution in building the hardware security and trust community. Notably, he was an individual member of the VSIA intellectual property protection (IPP) development working group (2001) and contributed to VSIA’s IPP standards; he published the first book (2003) on hardware security, Intellectual Property Protection in VLSI Designs: Theory and Practice, based on his Ph.D. dissertation (2000); he developed a MOOC of hardware security on Coursera (2014); he co-founded the AsianHOST symposium (2016) and the IEEE CEDA hardware security and trust technique committee (HSTTC, 2020). Since October 2021, he has been working as a program director in the NSF Secure and Trustworthy Cyberspace (SaTC) program. He is a fellow of IEEE.
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Travis Humble

Bio: Travis Humble is director of the Department of Energy’s Quantum Science Center, a Distinguished Scientist at Oak Ridge National Laboratory, and director of the lab’s Quantum Computing Institute. Travis leads the development of new quantum technologies and infrastructure to impact the DOE mission of scientific discovery. Travis is also editor-in-chief for ACM Transactions on Quantum Computing and co-chair of the IEEE Quantum Initiative. Travis holds a joint faculty appointment with the University of Tennessee Bredesen Center for Interdisciplinary Research and Graduate Education to work with students in developing energy-efficient computing solutions. Travis received a doctorate in theoretical chemistry from the University of Oregon before joining ORNL in 2005.
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Len Orlando

Bio: Len joined Ansys in January of this year to be part of the Ansys Government Initiatives business unit as a senior business development executive. Within Ansys he focused on supporting opportunities within the federal, aerospace, and defense marketplace and pursing strategic initiatives for Mission to Microelectronics, Microelectronics Security, and multi-physics simulation synthetic augmentation for defense relevant environments. Len has over 21 years within the federal Microelectronics industry starting as a designer, then project and team lead, before pursuing research activities as a subject matter expert on DARPA, Office of the Secretary of Defense, and Air Force trust, assurance, and security related microelectronics programs.
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