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Advance Program
Keynote 1: Thoughts on Edge Intelligence
(Grand Ballroom B-D, 9:00 - 10:00, Thursday, May 9)
Marilyn Wolf, Georgia Tech
Bio:
Dr. Marilyn Wolf is Farmer Distinguished Chair in Embedded Computing Systems and GRA Eminent
Scholar at the Georgia Institute of Technology. She received her BS, MS, and PhD in electrical engineering from
Stanford University in 1980, 1981, and 1984. She was with AT&T Bell Laboratories from 1984 to 1989 and was on the
faculty of Princeton University from 1989 to 2007. Her research interests include cyber-physical systems,
Internet-of-Things, embedded computing, embedded computer vision, and VLSI systems. She has received the IEEE Computer
Society Harry Goode Memorial Award, the ASEE Terman Award, and IEEE Circuits and Systems Society Education Award.
She is a Fellow of the IEEE and ACM.
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Keynote 2: Strategies for Supply Chain Hardware Security
(Grand Ballroom B-D, 12:00 - 1:10, Thursday, May 9)
Keith Rebello, DARPA
Abstract:
Globalization of the electronics supply chain has increased the Department of Defense’s (DoD) reliance on parts sourced
from untrusted locations. The rising complexity of the supply chain has made it easier for adversaries to compromise
commercial-off-the-shelf (COTS) parts used within DoD systems. Recently, Bloomberg reported that a hardware implant
allowed backdoor access to Supermicro servers in over 30 U.S. companies. Similar types of hardware tampering threats
could impact COTS systems used across the entire DoD enterprise.
Today, commercial systems undergo limited software installation and testing with little to
no hardware screening before fielding. A technology solution that rapidly detects adversarial
changes to COTS systems at the hardware level prior to installation and then actively monitors these systems
once installed is needed.
In this talk, we focus on strategies to detect and protect fielded systems
from hardware supply chain Trojans. This is particularly challenging as the COTS nature of the systems
prevents our control of the supply chain and even the very designs we wish to secure. Current cybersecurity
countermeasures focus on monitoring the system at the root or user software level or look for behavioral
changes at the integrated circuit level. As the complexity of circuit boards rise and the trustworthiness
of components is called more into question these techniques break down. One potential approach to overcoming
these monitoring limitations is to ensure monitoring is happening at the lowest hardware levels possible and
with a systems level approach instead of focusing on point solutions in individual integrated circuits. By
applying machine learning techniques to the system, a non-invasive hardware watchdog could monitor side-channel
signatures, network and bus traffic, memory, distributed hardware performance counters, etc. to learn a
baseline for normal operation. Then in real time, the system can adjust and take action when deviations from
the norm are encountered. System-level monitoring at the hardware level will offer a reliable method to
effectively protect and defend systems post-installation
Bio:
Mr. Keith Rebello joined DARPA in October 2018 as a program manager in the
Microsystems Technology Office (MTO). His research interests include the development of novel materials,
devices, and architectures for artificial intelligence, space, and cyber operations.
Recently, Mr. Rebello served as the technical director for emerging technologies
and technical lead for emerging threats in the Office of the Under Secretary of Defense for Intelligence
while on loan from the Johns Hopkins University Applied Physics Laboratory (JHU/APL)’s Cyber Operations
Mission Area. While at JHU/APL, he served as a program manager supporting the Navy’s next generation submarine
launched ballistic missile system, led the Office of the Secretary of Defense’s Prompt Global Strike
Integrated Product Teams developing hypersonic weapons technology, and established a research group focused
on microelectromechanical systems and ultra-low power integrated circuits.
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Keynote 3: Automatic Implementation of Secure Silicon
(Grand Ballroom B-D, 9:00 - 10:00, Friday, May 10)
Serge Leef, DARPA
Bio:
Mr. Serge Leef joined DARPA in August 2018 as a program manager in the Microsystems Technology
Office (MTO). His research interests include computer architecture, simulation, synthesis, semiconductor intellectual
property (IP), cyber-physical modeling, distributed systems, secure design flows, and supply chain management. He is also
interested in the facilitation of startup ecosystems and business aspects of technology. Leef came to DARPA from Mentor,
a Siemens Business where from 2010 until 2018 he was a Vice President of New Ventures, responsible for identifying and
developing technology and business opportunities in systems-oriented markets. Additionally, from 1999 to 2018, he served as a
division General Manager, responsible for defining strategies and building successful businesses around design automation
products in the areas of hardware/software co-design, multi-physics simulation, IP integration, SoC optimization, design
data management, automotive/aerospace networking, cloud-based electronic design, Internet of Things (IoT) infrastructure,
and hardware cybersecurity. Prior to joining Mentor, he was responsible for design automation at Silicon Graphics, where
he and his team created revolutionary, high-speed simulation tools to enable the design of high-speed 3D graphics chips,
which defined the state-of-the-art in visualization, imaging, gaming, and special effects for a decade. Prior to that, he
managed a CAE/CAD organization at Microchip and developed functional and physical design and verification tools for major
8- and 16-bit microcontroller and microprocessor programs at Intel. Leef received his Bachelor of Science degree in electrical
engineering and Master of Science degree in computer science from Arizona State University. He has served on corporate, state,
and academic advisory boards, delivered numerous public speeches, and holds two patents
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Keynote 4: Processing Data Where It Makes Sense in Modern Computing Systems:
Enabling In-Memory Computation
(Grand Ballroom B-D, 12:00 - 1:10, Friday, May 10)
Onur Mutlu, ETH Zurich
Abstract:
Today's systems are overwhelmingly designed to move data to
computation. This design choice goes directly against at least three
key trends in systems that cause performance, scalability and energy
bottlenecks: 1) data access from memory is already a key bottleneck as
applications become more data-intensive and memory bandwidth and
energy do not scale well, 2) energy consumption is a key constraint in
especially mobile and server systems, 3) data movement is very
expensive in terms of bandwidth, energy and latency, much more so than
computation. These trends are especially severely-felt in the
data-intensive server and energy-constrained mobile systems of today.
At the same time, conventional memory technology is facing many
scaling challenges in terms of reliability, energy, and
performance. As a result, memory system architects are open to
organizing memory in different ways and making it more intelligent, at
the expense of slightly higher cost. The emergence of 3D-stacked
memory plus logic, the adoption of error correcting codes inside the
latest DRAM chips, and intelligent memory controllers to solve the
RowHammer problem are an evidence of this trend.
In this talk, I will discuss some recent research that aims to
practically enable computation close to data. After motivating trends
in applications as well as technology, we will discuss at least two
promising directions: 1) performing massively-parallel bulk operations
in memory by exploiting the analog operational properties of DRAM,
with low-cost changes, 2) exploiting the logic layer in 3D-stacked
memory technology in various ways to accelerate important
data-intensive applications. In both approaches, we will discuss
relevant cross-layer research, design, and adoption challenges in
devices, architecture, systems, applications, and programming
models. Our focus will be the development of in-memory processing
designs that can be adopted in real computing platforms and real
data-intensive applications, spanning machine learning, graph
processing, data analytics, and genome analysis, at low cost. If time
permits, we will also discuss and describe simulation and evaluation
infrastructures that can enable exciting and forward-looking research
in future memory systems, including Ramulator and SoftMC.
Bio:
Dr. Onur Mutlu is a Professor of Computer Science at ETH Zurich. He is
also a faculty member at Carnegie Mellon University, where he
previously held the Strecker Early Career Professorship. His current
broader research interests are in computer architecture, systems,
hardware security, and bioinformatics. A variety of techniques he,
along with his group and collaborators, has invented over the years
have influenced industry and have been employed in commercial
microprocessors and memory/storage systems. He obtained his PhD and MS
in ECE from the University of Texas at Austin and BS degrees in
Computer Engineering and Psychology from the University of Michigan,
Ann Arbor. He started the Computer Architecture Group at Microsoft
Research (2006-2009), and held various product and research positions
at Intel Corporation, Advanced Micro Devices, VMware, and Google. He
received the inaugural IEEE Computer Society Young Computer Architect
Award, the inaugural Intel Early Career Faculty Award, US National
Science Foundation CAREER Award, Carnegie Mellon University Ladd
Research Award, faculty partnership awards from various companies, and
a healthy number of best paper or "Top Pick" paper recognitions at
various computer systems, architecture, and hardware security
venues. He is an ACM Fellow "for contributions to computer
architecture research, especially in memory systems", IEEE Fellow for
"contributions to computer architecture research and practice", and an
elected member of the Academy of Europe (Academia Europaea). For more
information, please see his webpage at
https://people.inf.ethz.ch/omutlu/.
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Keynote 5: Innovations in IoT for a Safe, Secure, and Sustainable Future
(Grand Ballroom B-D, 11:00 - 12:00, Friday, May 11)
Swarup Bhunia, University of Florida
Bio:
Dr. Swarup Bhunia is a preeminence professor of cybersecurity and Steven Yatauro
endowed faculty fellow at the department of Electrical and Computer Engineering at University of Florida,
USA. Earlier he was appointed as the T. and A. Schroeder associate professor of Electrical Engineering and Computer
Science at Case Western Reserve University, Cleveland, USA. He has over twenty years of research and development experience
with 250+ publications in peer-reviewed journals and premier conferences and nine authored/edited books. His research interests
include hardware security and trust, adaptive nanocomputing, bio-implantable systems, and novel test methodologies. Dr. Bhunia
received IBM Faculty Award (2013), National Science Foundation career development award (2011), Semiconductor Research
Corporation Inventor Recognition Award (2009), and SRC technical excellence award (2005) as a team member, and several best paper
awards/nominations. He is co-founding editor-in-chief of the Springer journal on hardware and systems security. He has been
serving as an associate editor of IEEE Transactions on CAD, IEEE Transactions on Multi-Scale Computing Systems, Journal of
Electronic Testing: Theory and Applications, Journal of Low Power Electronics, and IEEE Design & Test for Computers. He has served
as associate Editor for ACM Journal on Emerging Technologies in Computing Systems (JETC). Additionally, Dr. Bhunia has served as
guest editor of IEEE Transactions on Emerging Topics in Computing (2017), IEEE Computer Magazine (2016), IEEE Design & Test of
Computers (2010, 2013), IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2014), and ACM Journal on Emerging
Technologies in Computing Systems (2012). He has served as general chair of IEEE HOST 2017, Program Chair of IEEE HOST 2016, IEEE
NANOARCH 2013, IEEE VDAT 2014, and IEEE HOST 2015; vice program chair of IEEE HOST 2015 and IEEE IMS3TW 2011; and in the program
committee of number of IEEE/ACM conferences. Dr. Bhunia received his PhD from Purdue University on energy-efficient and robust
electronics, the B.E. (Hons.) from Jadavpur University, Kolkata, India, and the M.Tech. degree from the Indian Institute of Technology
(IIT), Kharagpur, India. He is a member of ACM and senior member of IEEE.
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Technical Session 1
Thursday
May 9
10:20 - 12:00
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Tech session 1: Design and Integration of Hardware Security Primitives
(Salon F)
Chair: Mehran Mozaffari Kermani, University of South Florida, USA
(16, 42, 50, 55, 74)
LPN-based Device Authentication Using Resistive Memory
Md Tanvir Arafin, Haoting Shen, Mark Tehranipoor and Gang Qu
Leveraging On-Chip Voltage Regulators Against Fault Injection Attacks
Ali Vosoughi and Selcuk Kose
On the Theoretical Analysis of Memristor based True Random Number Generator
(Best Paper Award Candidate)
Mesbah Uddin, Md Sakib Hasan and Garrett Rose
Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans
Dominik Šišejković, Farhad Merchant, Rainer Leupers, Gerd Ascheid and Volker Kiefer
Lightweight Authenticated Encryption for Network-on-Chip Communications
Julian Harttung, Elke Franz, Paul Walther and Sadia Moriam
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Technical Session 2
Thursday
May 9
1:10 - 2:30
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Tech session 2: VLSI Circuits and Power Aware Design
(Salon E)
Chair: Abhronil Sengupta, Pennsylvania State University, USA
(33, 58, 61, 137)
Design of a low-power and small-area approximate multiplier using first the approximate and then the accurate compression method
Tongxin Yang, Tomoaki Ukezono and Toshinori Sato
GraphiDe: A Graph Processing Accelerator leveraging In-DRAM-Computing
(Best Paper Award Candidate)
Shaahin Angizi and Deliang Fan
An Efficient Time-based Stochastic Computing Circuitry Employing Neuron-MOS
Tati Erlina, Yan Chen, Renyuan Zhang and Yasuhiko Nakashima
Monolithic 8x8 SiPM with 4-bit Current-Mode Flash ADC with Tunable Dynamic Range
Vikas Vinayaka, Sachin P Namboodiri, Shadden Abdalla, Bryan Kerstetter, Francisco Mata-Carlos, Daniel Senda, James Skelly, Angsuman Roy and R. Jacob Baker
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Technical Session 3
Thursday
May 9
1:10 - 2:30
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Tech session 3: : VLSI for Machine Learning and Artificial Intelligence
(Salon F)
Chair: Avesta Sasan, George Mason University, USA
(8, 31, 67, 102)
A Systolic SNN Inference Accelerator and its Co-optimized Software Framework
Shasha Guo, Lei Wang, Shuquan Wang, Yu Deng, Zhijie Yang, Shiming Li, Zhige Xie and Qiang Dou
Dynamic Beam Width Tuning for Energy-Efficient Recurrent Neural Networks
Daniele Jahier Pagliari, Francesco Panini, Enrico Macii and Massimo Poncino
Efficient Softmax Hardware Architecture for Deep Neural Networks
Gaoming Du, Chao Tian, Zhenmin Li, Duoli Zhang, Yongsheng Yin and Yiming Ouyang
HSIM-DNN: Hardware Simulator for Computation-, Storage- and Power-Efficient Deep Neural Networks
Mengshu Sun, Pu Zhao, Yanzhi Wang, Naehyuck Chang and Xue Lin
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Technical Session 4
Thursday
May 9
4:40 - 6:00
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Tech session 4: Next Generation Interconnect: Architecture to Physical Design
(Salon E)
Chair: Selcuk Kose, University of South Florida, USA
(15, 127, 129, 132)
An Area-Efficient Iterative Single-Precision Floating-Point Multiplier Architecture for FPGA
Sunwoong Kim and Rob Rutenbar
An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits Optimization
(Best Paper Award Candidate)
Zhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang, Jian Wang and Jinmei Lai
Low Voltage Clock Tree Synthesis with Local Gate Clusters
Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman
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Technical Session 5
Friday
May 10
10:20 - 12:00
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Tech session 5: Designing robust VLSI circuits. From approximate computing to hardware security
(Salon E)
Chair: Ian Harris, UC Irvine, USA
Co-Chair: Martin Margala, University of Massachusetts Lowell, USA
(126, 139, 19, 36, 64)
TOIC: Timing Obfuscated Integrated Circuits
Mahabubul Alam, Swaroop Ghosh and Sujay Sheshagiri Hosur
Design for eliminating operation specific power signatures from digital logic
(Best Paper Award Candidate)
Md Badruddoja Majumder, Md Sakib Hasan, Aysha Shanta, Mesbah Uddin and Garrett Rose
Non-Uniform Temperature Distribution in Interconnects and Its Impact on Electromigration
Ali Abbasinasab and Malgorzata Marek-Sadowska
Fault Classification and Coverage of Analog Circuits using DC Operating Point and Frequency Response Analysis
Sayandeep Sanyal, Shan Pavan Pani Krishna Garapati, Amit Patra, Pallab Dasgupta and Mayukh Bhattacharya
Crash Skipping: A Minimal-Cost Framework for Efficient Error Recovery in Approximate Computing Environments
(Best Paper Award Candidate)
Yan Herms and Yanjing Li
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Technical Session 6
Friday
May 10
1:10 - 2:30
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Tech session 6: Emerging Computing & Post-CMOS Technologies
(Salon E)
Chair: Yue Zhang, Beihang University, China
Co-Chair: Sorin Cotofana, Delft University of Technology, Netherland
(52, 72, 90, 111)
Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI
Hao Cai, Menglin Han, Weiwei Shan, Jun Yang, You Wang, Wang Kang and Weisheng Zhao
Low Cost Hybrid Spin-CMOS Compressor for Stochastic Neural Networks
Bingzhe Li, Jiaxi Hu, M.Hassan Najafi, Steven Koester and David Lilja
Functionally Complete Boolean Logic and Adder Design Based on 2T2R RRAMs for Post-CMOS In-Memory Computing
Linus Witschen, Hassan Ghasemzadeh Mohammadi, Matthias Artmann and Marco Platzner
Jump Search: A Fast Technique for the Synthesis of Approximate Circuits
Zongxian Yang, Yixiao Ma and Lan Wei
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Technical Session 7
Friday
May 10
1:10 - 2:30
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Tech session 7: Physical Design and Obfuscation
(Salon F)
Chair: Jianlei Yang, Beihang University, China
Co-Chair: Xiang Chen, George Mason University, USA
(1, 17, 86, 109)
SAT-Based Placement Adjustment of FinFETs inside Unroutable Standard Cells Targeting Feasible DRC-Clean Routing
Anton Sorokin and Nikolay Ryzhenko
A Scalable and Process Variation-Aware NVM-FPGA Placement Algorithm
(Best Paper Award Candidate)
Chengmo Yang and Yuan Xue
Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA
Bo Hu, Jingxiang Tian, Mustafa Shihab, Gaurav Rajavendra Reddy, William Swartz, Yiorgos Makris, Benjamin Carrion Schaefer and Carl Sechen
HydraRoute: A Novel Approach to Circuit Routing
Mohammad Khasawneh and Patrick Madden
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Technical Session 8
Friday
May 10
4:40 - 6:00
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Tech session 8: Quantum Circuits and Emerging Technologies
(Salon E)
Chair: Yanzhi Wang, Northeastern University, USA
(10, 46, 18, 40)
Balanced Factorization and Rewriting Algorithms for Synthesizing Single Flux Quantum Circuits
Ghasem Pasandi and Massoud Pedram
A Majority Logic Synthesis Framework for Adiabatic Quantum-Flux-Parametron Superconducting Circuits
Ruizhe Cai, Olivia Chen, Ao Ren, Ning Liu, Caiwen Ding, Nobuyuki Yoshikawa and Yanzhi Wang
A Processing-In-Memory Implementation of SHA-3 Using a Voltage-Gated Spin Hall-Effect Driven MTJ-based Crossbar
Chengmo Yang and Zeyu Chen
Exploring Processing In-Memory for Different Technologies
Saransh Gupta, Mohsen Imani and Tajana Rosing
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Technical Session 9
Saturday
May 11
1:10 - 2:30
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Tech session 9: Towards Fast, Efficient, and Robust Memory
(Salon F)
Chair: Inna Partin-Vaisband, University of Illinois at Chicago, USA
(43, 65, 78, 99)
BLADE: A BitLine Accelerator for Devices on the Edge
William Simon, Yasir Qureshi, Alexandre Levisse, Marina Zapater and David Atienza
Enhancing the Lifetime of Non-volatile Caches by Exploiting Module-Wise Write Restriction
Sukarn Agarwal and Hemangee K. Kapoor
Mitigating the Performance and Quality of Parallelized Compressive Sensing Reconstruction Using Image Stitching
Mahmoud Namazi, Hosein Makrani and Zhi Tian
Towards Optimizing Refresh Energy in embedded-DRAM Caches using Private Blocks
Sheel Sindhu Manohar, Sukarn Agarwal and Hemangee K. Kapoor
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Microelectronic Systems Education Workshop
Saturday
May 11
9:00 - 10:50
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Microelectronic Systems Education Workshop
(Salon F)
Chair: Tina Hudson, Rose Hulman Institute of Technology, USA
Co-Chair: Bradley Minch, Olin College, USA
(12, 97, 113, 125)
Extending Student Labs with SMT Circuit Implementation
Erik Brunvand
Teaching the Next Generation of Cryptographic Hardware Design to the Next Generation of Engineers
(Best MSE Track Paper Award)
Aydin Aysu
A Web-based Remote FPGA Laboratory for Computer Organization Course
Han Wan, Kangxu Liu, Jiazhen Lin and Xiaopeng Gao
System-on-a-Chip Design as a Platform for Teaching Design and Design Flow Integration
Jacob Covey and Mark Johnson
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Special Session 1
Thursday
May 9
10:20 - 12:00
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Special session 1: In-Memory Processing for Future Electronics
(Salon E)
Organizers: Ronald F. DeMara (University of Central Florida); Wang Kang (Beihang University)
Digital and Analog-Mixed-Signal In-Memory Processing in CMOS SRAM
Akhilesh Ramlaut Jaiswal (Purdue University); Kaushik Roy (Purdue University)
Ferroelectric FET based In-Memory Computing for Few-Shot Learning
Ann Franchescha Laguna (University of Notre Dame); Xunzhao Yin (University of Notre Dame); Dayane Reis (University of Notre Dame); Michael Niemier (University of Notre Dame); X. Sharon Hu (University of Notre Dame)
True In-memory Computing with the CRAM: From Technology to Applications
Masoud Zabihi (University of Minnesota); Zhengyang Zhao (University of Minnesota); Zamshed I. Chowdhury (University of Minnesota); Salonik Resch (University of Minnesota); Mahendra DC (University of Minnesota); Thomas Peterson (University of Minnesota); Ulya R. Karpuzcu (University of Minnesota); Jian-Ping Wang (University of Minnesota); Sachin S. Sapatnekar (University of Minnesota)
An Overview of In-memory Processing with Emerging Non-volatile Memory for Data-intensive Applications
Bing Li (Duke University); Bonan Yan (Duke University); Hai Li (Duke University)
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Special Session 2
Thursday
May 9
4:40 - 6:00
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Special session 2: Approximate Computing Systems Design: Energy Efficiency and Security Implications
(Salon F)
Organizer: Qiaoyan Yu (University of New Hampshire); Michel Kinsy (Boston University)
Security Threats in Approximate Computing Systems
Pruthvy Yellu (University of New Hampshire); Qiaoyan Yu (University of New Hampshire); Novak Boskov (Boston University); Michel Kinsy (Boston University)
Understanding Approximate Adders and Multipliers Optimized under Different Design Constraints
Honglan Jiang (University of Alberta and Tsinghua University); Francisco Javier Hernandez Santiago (University of Alberta); Mohammad Saeed Ansari (University of Alberta); Bruce Cockburn (University of Alberta); Leibo Liu (Tsinghua University); Fabrizio Lombardi (Northeastern University); Jie Han (University of Alberta)
Approximate Communication Strategies for Energy-Efficient and High Performance NoC: Opportunities and Challenges
Md Farhadur Reza (Virginia Polytechnic Institute and State University); Paul Ampadu (Virginia Polytechnic Institute and State University)
Information Hiding Behind Approximate Computation
Ye Wang (Harbin Institute of Technology); Qian Xu (University of Maryland); Gang Qu (University of Maryland); Jian Dong (Harbin Institute of Technology)
MLPrivacyGuard: Defeating Confidence Information based Model Inversion Attacks on Machine Learning Systems
Tiago Alves (Universidade do Estado do Rio de Janeiro); Felipe M.G. França (Universidade Federal do Rio de Janeiro); Sandip Kundu (University of Massachusetts, Amherst)
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Special Session 3
Friday
May 10
10:20 - 12:00
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Special session 3: Recent Advances in Near and In-Memory Computing Circuit and Architecture for Artificial Intelligence and Machine Learning
(Salon F)
Organizer: Mingoo Seok (Columbia University); Tinoosh Mohsenin (University of Maryland – Baltimore County)
XNOR-SRAM: In-Bitcell Computing SRAM Macro based on the Resistive Computing Mechanism
Zhewei Jiang (Columbia University); Shihui Yin (Arizona State University); Jae-sun Seo (Arizona State University); Mingoo Seok (Columbia University)
Efficient Process-in-Memory Architecture Design for Unsupervised GAN-based deep learning using ReRAM
Fan Chen (Duke University); Linghao Song (Duke University); Hai Li (Duke University); Yiran Chen (Duke University)
DigitalPIM: Digital-based Processing In-Memory for Big Data Acceleration
Mohsen Imani (UC San Diego); Saransh Gupta (UC San Diego); Yeseong Kim (UC San Diego); Minxuan Zhou (UC San Diego); Tajana Rosing (UC San Diego)
In-memory processing based on time-domain circuit
Yuyao Kong (Southeast University); Jun Yang (Southeast University)
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Special Session 4
Friday
May 10
4:40 - 6:00
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Special session 4: Opportunities and Challenges for Emerging Monolithic 3D Integrated Circuits
(Salon F)
Organizer: Emre Salman (Stony Brook University); Ayse Coskun (Boston University); Vasileios Pavlidis (University of Manchester)
An Overview of Thermal Challenges and Opportunities for Monolithic 3D Ics
Prachi Shukla (Boston University); Ayse K. Coskun (Boston University); Vasilis Pavlidis (University of Manchester); Emre Salman (Stony Brook University)
Logic Monolithic 3D ICs: PPA Benefits and EDA Tools Necessary
Sai Pentapati (Georgia Tech); Sung Kyu Lim (Georgia Tech)
Investigation and Trade-offs in 3DIC Partitioning Methodologies
Nikolaos Sketopoulos (University of Thessaly); Christos P. Sotiriou (University of Thessaly); Vasileios Samaras (University of Thessaly)
Test and Design-for-Testability Solutions for Monolithic 3D Integrated Circuits
Abhishek Koneru (Duke University); Krishnendu Chakrabarty (Duke University)
N3XT Monolithic 3D Energy-Efficient Computing Systems
Mohamed M. Sabry (Nanyang Technological University)
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Special Session 5
Saturday
May 11
1:10 - 2:30
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Special session 5: Robust IC Authentication and Protected Intellectual Property: A Special Session on Hardware Security
(Salon E)
Organizers: Avesta Sasan (George Mason University)
How to Generate Robust Keys from Noisy DRAM
Fatemeh Tehranipoor (San Fransisco State University); Nima Karimian (San José State University)
Threats on Logic Locking: A Decade Later Speaker
Kimia Zamiri Azar (George Mason University); Hadi Mardani Kamali (George Mason University); Houman Homayoun (George Mason University); Avesta Sasan (George Mason University)
Making LUT Obfuscation a Practical Solution: Breaking the Design and Security Trade-O_s Using Custom LUT-based Obfuscation
Gaurav Kolhe (George Mason University); Sai Manoj P D (George Mason University); Setareh Rafatirad (George Mason University); Hadmid Mahmoodi (Logimem Co.); Avesta Sasan (George Mason University); Houman Homayoun (George Mason University)
Securing Analog/Mixed-Signal Integrated Circuits Through Shared Dependencies
Kyle Juretus (Drexel University); Vaibhav Venugopal Rao (Drexel University); Ioannis Savidis (Drexel University)
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Special Session 6
Saturday
May 11
2:40 - 4:00
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Special session 6: Neuromorphic Computing and Deep Neural Network
(Salon E)
Organizers: Yanzhi Wang (Northeastern University); Anup Das (Drexel University); Tinoosh Mohsenin (University of Maryland Baltimore County)
Design Methodology for Embedded Approximate Artificial Neural Networks
Adarsha Balaji (Drexel University); Salim Ullah (Technische Universität Dresden); Anup Das (Drexel University); Akash Kumar (Technische Universität Dresden)
Exploration of Segmented Bus As Scalable Global Interconnect for Neuromorphic Computing
Adarsha Balaji (Drexel University); Yuefeng Wu (Stichting IMEC Nederland); Anup Das (Drexel University); Francky Catthoor (IMEC Belgium and KU Leuven); Siebren Schaafsma (Stichting IMEC Nederland)
ADMM-based Weight Pruning for Real-Time Deep Learning Acceleration on Mobile Devices
Hongjia Li (Northeastern University); Ning Liu (Northeastern University); Xiaolong Ma (Northeastern University); Tianyun Zhang (Syracuse University); Shaokai Ye (Syracuse University); Sheng Lin (Northeastern University); Xue Lin (Northeastern University); Wenyao Xu (University at Buffalo); Yanzhi Wang (Northeastern University)
On the use of Deep Autoencoders for Efficient Embedded Reinforcement Learning
Bharat Prakash (University of Maryland Baltimore County); Mark Horton (University of Maryland Baltimore County); Nicholas R. Waytowich (US Army Research Laboratory); William David Hairston (US Army Research Laboratory); Tim Oates (University of Maryland Baltimore County); Tinoosh Mohsenin (University of Maryland Baltimore County)
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Panel Session 1
Thursday
May 9
3:30 - 4:30
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Panel 1: Emerging Technologies for Right-Provisioned IoT Computing
(Grand Ballroom B-D)
Moderator: Tosiron Adegbija (University of Arizona)
Panelist:
Chengmo Yang (University of Delaware)
Vinu Vijay Kumar (Google)
Amir Rahmani (University of California, Irvine)
Himanshu Thapliyal (University of Kentucky)
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Panel Session 2
Friday
May 10
3:30 - 4:30
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Panel 2: Trusted and Assured Microelectronics: Design For Security
(Grand Ballroom B-D)
Moderator: Michel A. Kinsy (Boston University)
Panelist:
Sohrab Aftabjahani (Intel Artificial Intelligence Product Group)
Brian Cohen (Institute of Defense Analysis)
Adam Kimura (Battelle)
Gang Qu (University of Maryland College Park)
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Poster Sessions
May 9/10
2:30 - 3:30
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(Salon B-D Foyer)
Chair: Emre Salman, Stony Brook University, USA
(3, 5, 6, 13, 22, 24, 27, 29, 32, 35, 37, 71, 75, 77, 80, 98, 100, 103, 108, 114, 117, 119, 121, 122, 128, 130, 135, 136, 141)
UPIM : Unipolar Switching Logic for High Density Processing-in-Memory Applications
Joonseop Sim
Fence-Region-Aware Mixed-Height Standard Cell Legalization
Sanggi Do, Mingyu Woo and Seokhyeong Kang
A Case for Heterogeneous Network-on-Chip Based H.264 Video Decoders
Milad Ghorbani Moghaddam and Cristinel Ababei
A 16b Clockless Digital-to-Analog Converter with Ultra-Low-Cost Poly Resistors Supporting Wide-Temperature Range from -40℃ to 85℃
Xuedi Wang, Xueqing Li, Longqiang Lai and Huazhong Yang
A Skyrmion Racetrack Memory based Computing In-memory Architecture for Binary Neural Convolutional Network
Yu Pan, Peng Ouyang, Yinglin Zhao, Shouyi Yin, Youguang Zhang, Shaojun Wei and Weisheng Zhao
TASecure: Temperature-Aware Secure Deletion Scheme for Solid State Drives
Bingzhe Li and David Du
An Asymmetric Dual Output On-Chip DC-DC Converter for Dynamic Workloads
Xingye Liu and Paul Ampadu
CNNWire: Boosting Convolutional Neural Network with Winograd on ReRAM based Accelerators
Jilan Lin, Shuangchen Li, Xing Hu, Lei Deng and Yuan Xie
Feed-Forward XOR PUFs: Reliability and Attack-Resistance Analysis
Satya Venkata Sandeep Avvaru and Keshab Parhi
Exploring Design Trade-offs in Fault-Tolerant Behavioral Hardware Accelerators
Zhiqi Zhu, Farah Naz Taher and Benjamin Carrion Schafer
Automatic Extraction of Requirements from State-based Hardware Designs for Runtime Verification
Minjun Seo and Roman Lysecky
MirrorCache: An Energy-Efficient Relaxed Retention L1 STTRAM Cache
Kyle Kuan and Tosiron Adegbija
Design and Evaluation of DNU-Tolerant Registers for Resilient Architectural State Storage
Faris S. Alghareb and Ronald F. DeMara
Automated Analysis of Virtual Prototypes at Electronic System Level
Mehran Goli, Muhammad Hassan, Daniel Grosse and Rolf Drechsler
Dynamic Physically Unclonable Functions
Wenjie Xiong, André Schaller, Stefan Katzenbeisser and Jakub Szefer
RDTA: An Efficient Routability-Driven Track Assignment Algorithm
Genggeng Liu, Zhen Zhuang, Wenzhong Guo and Ting-Chi Wang
EraseMe: A Defense Mechanism against Information Leakage through GPU Memory
Hongyu Fang, Milos Doroslovacki and Guru Venkataramani
A Statistical Current and Delay Model Based on Log-Skew-Normal Distribution for Low Voltage Region
Peng Cao, Jiangping Wu, Zhiyuan Liu, Jingjing Guo, Jun Yang and Longxing Shi
Enabling Approximate Storage through Lossy Media Data Compression
Brian Worek and Paul Ampadu
Thermal Fingerprinting of FPGA Designs through High-Level Synthesis
Jianqi Chen and Benjamin Carrion Schafer
Deep RNN-Oriented Paradigm Shift through BOCANet: Broken Obfuscated Circuit Attack
Fatemeh Tehranipoor, Nima Karimian, Mehran Mozaffari Kermani and Hamid Mahmoodi
STAT: Mean and Variance Characterization for Robust Inference of DNNs on Memristor-based Platforms
Baogang Zhang, Necati Uysal and Rickard Ewetz
LSM: Novel Low-Complexity Unified Systolic Multiplier over Binary Extension Field
Jiafeng Xie and Chiou-Yng Lee
Binarized Depthwise Separable Neural Network for Object Tracking in FPGA
Li Yang, Zhezhi He and Deliang Fan
An analytical-based hybrid algorithm for FPGA placement
Chengyu Hu, Qinghua Duan, Liran Hu, Peng Lu, Zhengjie Li, Meng Yang, Jian Wang and Jinmei Lai
Approximate Memory with Approximate DCT
Shenghou Ma and Paul Ampadu
AQuRate: MRAM-based Stochastic Oscillator for Adaptive Quantization Rate Sampling of Spectrally Sparse Signals
Soheil Salehi, Ramtin Zand, Alireza Zaeemzadeh, Nazanin Rahnavard and Ronald F. DeMara
Clockless Spin-based Look-Up Tables with Wide Read Margin
Soheil Salehi, Ramtin Zand and Ronald F. DeMara
A Hybrid Framework for Functional Verification using Reinforcement Learning and Deep Learning
Karunveer Singh, Rishabh Gupta, Vikram Gupta, Arash Fayyazi, Massoud Pedram and Shahin Nazarian
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GLSVLSI 2019 Webmaster
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