Banff, Alberta, Canada, May 10-12, 2017

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Department of Electrical and Computer Engineering

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The 27th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI) will be held in the beautiful Canadian Rockies. Original, unpublished papers describing research in the general areas of VLSI and hardware design are solicited. Stay tuned for more information.

In addition to the traditional topic areas of GLSVLSI listed below, papers are solicited for a special theme of Green Technologies for Computing and IoT Applications.




    The Best-Paper Award recipients are:


    Ruizhou Ding (Carnegie Mellon Univ.); Zeye Liu (Carnegie Mellon Univ.); Rongye Shi (Carnegie Mellon Univ.); Diana Marculescu (Carnegie Mellon Univ.); Shawn Blanton (Carnegie Mellon Univ.)

    for their paper titled:

    LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks

    Congratulations to the winners!


  • May 14th: Conference Statistics: 197 submissions, with an acceptance rate of 24.4% for regular papers (6 pages in the proceedings), and 12.2% for poster papers (4 pages in the proceedings).

Program Tracks:

Track 1: VLSI Design: ASIC and FPGA design, microprocessors/micro-architectures, embedded processors, analog/digital/mixed-signal systems, NoC, SoC, IoT, interconnects, memories.

Track 2: VLSI Circuits, and Power Aware Design: analog/digital/mixed-signal circuits, RF and communication circuits, chaos/neural/fuzzy-logic circuits, high-speed/low-power circuits, temperature estimation/optimization, power estimation/optimization.

Track 3: Computer-Aided Design (CAD): hardware/software co-design, high-level synthesis, logic synthesis, simulation and formal verification, layout, design for manufacturing, algorithms and complexity analysis.

Track 4: Testing, Reliability, and Fault-Tolerance: digital/analog/mixed-signal testing, reliability, robustness, static and dynamic defect- and fault-recoverability, variation-aware design.

Track 5: Emerging Computing, and Post-CMOS Technologies: nanotechnology, molecular and quantum computing, approximate and stochastic computing, sensor and sensor networks, post CMOS VLSI.

Track 6: Hardware Security: trusted IC, IP protection, hardware security primitives, reverse engineering, hardware Trojan, side-channel analysis, CPS and IoT security.

Track 7: Biochips, and Biological Systems: bio-inspired and neuromorphic circuits and systems, BioMEMs, lab-on-a-chip, biosensors, hardware and software solutions for medical diagnostics, CAD tools for biology and biomedical systems, implantable and wearable devices, systems and synthetic biology.


Important Dates

Paper Submission Deadline:

December 23 (ABSTRACT), January 6 (FULL PAPER), 2016 - EXTENDED

Acceptance Notification:

February 13, 2017

Camera-Ready Paper Due:

March 13, 2017


Paper Submission: Authors are invited to submit full-length (6 pages maximum), original, unpublished papers along with an abstract of at most 200 words.  To enable blind review, the author list should be omitted from the main document.  Previously published papers or papers currently under review for other conferences/journals should NOT be submitted and will not be considered.  Electronic submission in PDF format to the website is required.  Author and contact information (name, affiliation, mailing address, telephone, fax, e-mail) must be entered during the submission process.

Paper Format: Submissions should be in camera-ready two-column format, following the ACM proceedings specifications located at:

and the classification system detailed at:

Please use the ACM sigconf template if you are using Latex.

Paper Publication and Presenter Registration: Papers will be accepted for regular or poster presentation at the symposium.  Every accepted paper MUST have at least one author registered to the symposium by the time the camera-ready paper is submitted; at least one of the authors is also expected to attend the symposium and present the paper.

Paper Format: Submissions should be in camera-ready two-column format, following the ACM proceedings specifications located at: and the classification system detailed at:


This site is maintained by:
GLSVLSI 2017 Webmaster
Theo Theocharides (, University of Cyprus.